CMOS circuits are increasingly deployed in cryogenic environments, yet standard process design kits (PDKs) are typically validated only down to ~220 K, producing significant simulation errors at lower temperatures. This paper presents a compact modeling framework that augments an existing PDK with measurement-based corrections to the threshold voltage (VTH) and on-state drain current (ID). The temperature dependences of (VTH) and (ID) are extracted from a fabricated prototype transistor across the 12–300 K range rather than at a single cryogenic point. Compact voltage and current sources are then incorporated into standard MOSFET models to improve low-temperature accuracy without modifying the foundry-provided models. The framework is validated using a current-controlled ring oscillator biased by a proportional-to-absolute-temperature (PTAT) current source, fabricated in a 65 nm CMOS process. From 12 K to room temperature, measurements show up to a 6.45× improvement in the simulation accuracy of the oscillator's output frequency relative to a conventional PDK.
This brief presents a 3-D integrated 6–18 GHz reconfigurable filtering low-noise amplifier (LNA) using a GaAs pHEMT MMIC and a vertically stacked GaAs hyper-abrupt varactor die. The vertically integrated varactors are employed as the voltage-controlled tuning elements in the reconfigurable filtering networks, enabling wide-range passband tuning beyond that achievable with MMIC-compatible varactors. Two switch-selected reconfigurable filtering paths cover the 6–12 GHz and 12–18 GHz sub-bands, enabling continuous narrowband passband tuning within the two sub-bands across the overall operating range. The transmission-zero tuning behavior and the EM-extracted vertical-transition response are considered in the circuit/EM co-design. The fabricated stacked chip occupies 3.8 mm × 2.5 mm. Measured results show 28.5–32.5 dB gain, 0.9–1.25 dB NF, OP1dB above 15.2 dBm, and a typical out-of-band rejection of 40 dBc.
This work presents energy-efficient approximate multipliers based on two complementary types of approximate adders, one that underestimates and another that overestimates the result of addition. Owing to their simplified logic structures, these adders significantly reduce hardware cost. The main strength of the proposed approach lies in exploiting the complementary error behavior of these adders. When strategically placed within the partial product reduction stage of an approximate multiplier, their opposing error tendencies enable effective error compensation, resulting in a favorable balance between accuracy and hardware efficiency. Applying these adders to 8–11 least significant columns of an 8-bit multiplier yields substantial hardware improvements, including up to 53% reduction in delay, 82% reduction in energy consumption, and 76% reduction in area, while maintaining mean relative error distance (MRED) values between 3.4% and 12.1%. For similar accuracy levels, the proposed multipliers consistently outperform state-of-the-art approximate multipliers in terms of delay, power, and area. The architecture is scalable, allowing larger bit-width multipliers to be constructed iteratively from smaller configurations, with increasing hardware benefits observed at higher bit-widths for comparable normalized error levels. This work further evaluates the proposed multipliers in practical applications, including deep neural networks and image processing. When integrated into the fine-tuned ViT-Small vision transformer model, the design incurs only a 0.1% reduction in classification accuracy while achieving 37% energy and 40% area savings compared to an exact multiplier. Image multiplication and Sobel edge detection experiments also demonstrate high output quality, with PSNR and SSIM values exceeding 30 dB and 0.9, respectively.
Direct current (DC) microgrids have attracted increasing attention due to their high efficiency and compatibility with renewable sources and energy storage systems. However, existing cooperative and communication-efficient control schemes for power buffers still rely heavily on accurate system models, which may limit performance under parameter variations and topology changes. This paper develops a distributed data-driven dynamic event-triggered control framework for power buffers in DC microgrids. Historical state-input trajectories are used to characterize the interconnected system and synthesize the controller directly, thereby avoiding explicit model identification. A dynamic event-triggered mechanism (DETM) is introduced to reduce unnecessary transmissions, and a model-free co-design of structured feedback gains and triggering weights is established via Lyapunov theory, the S-procedure, and linear matrix inequalities (LMIs). The design is centralized offline but distributed online: stacked trajectories are used only for LMI synthesis, while the implemented law follows the prescribed communication sparsity. Simulation results show that the proposed method achieves fast energy and voltage regulation under load disturbances while reducing communication burden compared with model-based and periodic communication strategies. Additional robustness discussions are included for representative parameter-perturbation and topology-change cases.
This brief proposes a generalized iterative learning disturbance observer (GILDO) to handle complex disturbances consisting of slowly-varying and multi-periodic components. The observer employs a hierarchical serial-parallel learning structure that incorporates multiple learning channels with distinct time delays and exploits historical information from different periods, thereby enabling simultaneous estimation of both slowly-varying and periodic components. A systematic parameter tuning method is also provided to ease practical implementation. The stability of the observer error system is proven, and the error transfer function is used to characterize the estimation performance at target frequencies and their harmonics. Experimental results on a PMSM drive system demonstrate that the proposed method achieves effective attenuation of speed ripples induced by slowly-varying and periodic disturbances, while retaining a relatively low observer bandwidth.
Near-sensor smart sensing requires compact and energy-efficient hardware to support local deep neural network (DNN) inference under stringent power, latency, and accuracy constraints. Analog compute-in-memory (ACIM) exploits analogdomain multiply-accumulate (MAC) to improve computing density and energy efficiency, making it a promising hardware solution for low-power near-sensor smart sensing. However, existing ACIM architectures still suffer from two major limitations for near-sensor deployment: the power and latency overhead caused by cross-bank partial-sum (pSUM) accumulation and digital-domain non-MAC operations, and the computation accuracy degradation induced by analog circuit non-idealities. This brief presents Shuffle-CIM-NR, a shuffle-based charge-domain CIM architecture for low-power and robust near-sensor inference. By mapping shuffled convolution groups into individual CIM banks, Shuffle-CIM-NR eliminates cross-bank pSUM accumulation and enables one-shot 4-bit signed-weight/activation MAC operations. To further improve analog computing robustness, Shuffle-CIM-NR co-optimizes the activation input path, signed multi-bit MAC computation, and analog readout, while integrating batch-normalization (BN), activation, and quantization into the ADC. Implemented in TSMC 22-nm CMOS, the proposed architecture achieves an energy efficiency of 283.2 TOPS/W and an area efficiency of 2.73 TOPS/mm2 with excellent linearity, providing an efficient and robust CIM solution for near-sensor smart sensing applications.
Jitter-induced in-band noise in continuous-time bandpass delta-sigma modulators (CT-BPΔΣMs) arises from two distinct mechanisms: a quantization-driven contribution shaped by the noise transfer function (NTF), and a signal-dependent contribution governed by the normalized center frequency fc/fs. In single-bit implementations, where the quantization-driven contribution dominates, incorporating a bandpass finite impulse response (FIR) filter in the feedback DAC suppresses this noise while preserving the inherent linearity of single-bit architectures and maintaining robustness against out-of-band blockers. Once the quantization-driven contribution is suppressed, the remaining signal-dependent jitter floor can be further reduced by lowering fc/fs.
This brief presents a low-power down-conversion mixer targeting for fifth-generation (5G) new radio (NR) applications in the 26.5–29.5 GHz frequency range. The proposed architecture adopts a dual transconductance (Gm) boosting technique within the input transconductance stage to enhance performance under stringent power constraints. By integrating an auxiliary amplifier together with a transformer-based coupling network, the design achieves substantial Gm enhancement and noise-cancelled functionality while preserving a high conversion gain at reduced bias current levels. Fabricated in a 65-nm complementary metal–oxide–semiconductor process, the mixer attains a conversion gain of 13.7 dB and a single sideband noise figure of 8.6 dB. It further exhibits an input 1-dB compression point of –17.5 dBm and an input third-order intercept point of –7.1 dBm. Operating from a 1.2 V supply, the design consumes a bias current of 7.2 mA, offering a high-efficiency solution for millimeter-wave receiver front-end applications.
Vision Transformers (ViTs) deliver superior accuracy but incur prohibitive computational costs for on-device inference due to multiplication-intensive matrix operations. We present SHARP, a fine-tuning-free ViT accelerator that combines sensitivity-aware mixed quantization with a fully pipelined architecture. SHARP assigns one of three quantization schemes—INT, Power-of-Two, or Hybrid—to each static matrix multiplication based on layer-wise sensitivity analysis, replacing a substantial fraction of multiplications with hardware (HW)-efficient shift operations while preserving model accuracy. To effectively support this mixed quantization approach, SHARP introduces dedicated compute engines optimized for each quantization scheme and employs resource allocation-based pipeline balancing to eliminate bubbles and maximize throughput. Implemented on a Xilinx ZCU102 FPGA, SHARP achieves 69.34% Top-1 accuracy on DeiT-Tiny without fine-tuning and delivers 351.2 FPS at 31.38 FPS/W. Compared to CPU, SHARP demonstrates 26.8× and 26.3× improvements in FPS/W and GOPS/W, respectively.
This brief presents a single-ended impedance-matched four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for low-power memory interfaces, fabricated in 28-nm CMOS. A CML-assisted N-over-N driver is proposed to reduce power consumption and driver size by removing the extra design margin of the pull-up NMOS (PU-N) conventionally reserved for impedance matching. The remaining output swing and feed-forward equalization (FFE) are provided by an unstacked tailless CML path, which preserves output impedance matching during equalization. To mitigate the large PU-N overhead, a ZQ calibration scheme is proposed that eliminates the PU trimming margin while maintaining Z0 matching and a high ratio of level mismatch (RLM). The proposed TX achieves an energy efficiency of 0.38 pJ/bit/pin with 2-tap FFE and RLM of 99.7%, and occupies an active area of 0.006 mm2.
This brief proposes a compact reconfigurable switched-capacitor (SC) DC-DC converter targeting the miniaturization trend of internet of things (IoT) devices and dynamic voltage scaling (DVS) applications. The proposed topology utilizes only 21 switches and three flying capacitors (CFLY) to achieve step-down voltage conversion ratios (VCR) of 5:4/3/2/1, converting a 1.5 V input to a 0.16–1.19 V output. A soft VCR transition technique is employed to eliminate the hard-charging loss of the CFLY, while an all-NMOS switch implementation is adopted to minimize switching losses. Fabricated in a 180 nm CMOS process, the converter achieves a measured steady-state peak power conversion efficiency (PCE) of 93.7%, supporting a maximum output current of 240 mA. Under periodic VCR transitions at 100 kHz, an average conversion efficiency as high as 85% is attained.
This brief investigates the robustness of Chua’s chaotic oscillators when ideal passive components are replaced by their fractional-order equivalents — Constant Phase Elements (CPE). Starting from the canonical Chua’s circuit, we first verify its chaotic double-scroll behavior under standard conditions, and subsequently replace the nonlinear resistor RN with a flux-controlled memristor model RM, applying the appropriate impedance scaling. We show that the two variants are not independent dynamical systems, but are tied by an exact differential relation: the voltage and current waveforms of the RM oscillator correspond to time derivatives of the voltage and current waveforms of the RN oscillator. Hence, obtaining the RM response merely requires simulating the RN circuit, since its state-vector derivative is a by-product of numerical integration. Moreover, both the resistive and memristive versions of the circuit are then analyzed under CPE substitution of the inductor and capacitors, with the fractional order α varied from unity toward zero. Results show that reducing α below a threshold value causes the double-scroll attractor to change into another form, demonstrating that parasitic fractional-order properties of real inductors and capacitors can substantially modify — and ultimately destroy — deterministic chaos.
Electronic synapses are fundamental components of efficient, large-scale neuromorphic computing systems because they enable continuous weight modulation and hardware-level plasticity. The standard CMOS-based synaptic approach has been widely studied due to its superior process compatibility and high integration density. However, the existing design relies on impact ionization under a high electric field to generate carriers to finish conductance modulation through the back-gate effect, during which a fraction of hot carriers are injected into the gate oxide, inducing a decrease in the threshold voltage with nonlinear characteristics, thereby reducing the achievable conductance ratio and degrading the accuracy of neuromorphic computing. To address this limitation, we propose a MOSFET-based electronic synapse circuit that effectively prevents carrier injection into the gate oxide through an active substrate charge injection mechanism. By constructing a tunable current branch to implement charge injection into and release from the substrate, the synaptic conductance is regulated solely by the active injection branch, rather than being simultaneously affected by charge injection into the gate oxide as in the existing scheme. Therefore, this approach effectively enhances the conductance ratio. Simulation results indicate that the proposed electronic synapse achieves a conductance ratio of approximately 105, a coefficient of determination of R2 = 0.96 for the weight-update behavior, and nonlinearity factors of 0.09 and -0.26 for synaptic weight potentiation and depression, respectively, while exhibiting strong robustness against process and temperature variations.
A direct digital frequency synthesizer (DDFS) which requires high spurious-free dynamic range (SFDR) performance often faces significant hardware overhead, particularly in its reliance on dedicated multipliers within digital signal processing (DSP) slices or large lookup tables (LUTs) within block RAMs (BRAMs). This paper presents a multiplier-less, high-SFDR DDFS architecture that incorporates a novel 3-segment Adaptive Recoding CORDIC (ARC) design to improve convergence and SFDR under multiplier-less constraints. Furthermore, an Adaptive Upward Rounding Algorithm (AURA) is introduced as an empirically effective sub-LSB error compensation strategy, motivated by statistical error characteristics, which helps suppress truncation-related spurs with negligible hardware overhead. Implementation on an AMD Artix-7 FPGA demonstrates that the 17-bit high-precision model achieves an average SFDR of 119.65 dBc at a maximum clock frequency of 259.7 MHz, while the 15-bit resource-efficient variant provides 106.84 dBc SFDR at 269.5 MHz, both without using any DSP slices or BRAMs.
This brief proposes a simplified three-port resonant forward converter for low-power photovoltaic (PV) systems. The design aims to reduce power-stage component cost while ensuring sufficient regulation capability. Specifically, an auxiliary winding of the main resonant tank is magnetically coupled to the filtering inductor of the battery management circuit. This introduces phase-shift as an additional degree of freedom for gain adjustment, thereby eliminating the need for a dedicated pre-regulation stage. As a result, the proposed integration scheme reduces system complexity and power conversion stages, leading to improved power-board-level cost-effectiveness. Based on theoretical analysis, experimental results validate the proposed design.
This brief presents a 100-Gb/s voltage-mode (VM) digital-to-analog converter (DAC)-based transmitter (TX) that jointly optimizes output linearity and hardware efficiency through the co-design of a digital pre-distortion (DPD) encoder and a merged 4:1 MUX-driver topology. The proposed ideal-ramp-fitting-based DPD calibration eliminates the series resistor and minimizes the transistor size in the VM driver while maintaining high output linearity. This makes it feasible to merge the 4:1 MUX in the final stage to reduce the internal high-speed nodes, which is a pioneer attempt for the VM driver. Furthermore, the proposed DPD encoder reduces the storage resources required for the DPD code look-up table (LUT) by 30%. Fabricated in a 28-nm CMOS process, measurement results show that the TX can operate at 100 Gb/s four-level pulse amplitude modulation (PAM-4) signaling with analog and digital energy efficiencies of 1.66 pJ/b and 0.38 pJ/b, respectively.
The rapid proliferation of Internet-of-Things (IoT) applications has increased the demand for secure and efficient cryptographic processing in resource-constrained System-on-Chips (SoCs). This brief presents a compact and hardware-efficient Advanced Encryption Standard (AES) accelerator for RISC-V (RISCY) processors, integrated with a lightweight digital power-side-channel countermeasure. The proposed approach combines stall-induced trace desynchronization and activity equalization to disrupt power trace alignment and mitigate power attacks without relying on hardware-intensive techniques. The proposed design incurs ultra-low hardware overhead of only 0.27%/1.27% in area and 0.23%/−4.19% in power for the system/AES implementations, respectively, while preserving the critical-path delay. Security evaluation demonstrates strong leakage suppression, achieving Measurements to Disclosure (MTD) greater than 1 million, reducing the Signal-to-Noise Ratio (SNR) to 0.518 (< 1), maintaining Mutual Information (MI) in the milli-range, and satisfying the Test Vector Leakage Assessment (TVLA) criterion within the ±4.5 threshold. The proposed digital co-design provides a practical, low-overhead solution for secure AES acceleration in lightweight IoT platforms.
Eigenpair computation is fundamental to massive MIMO signal processing. This brief presents an eigenpair solver dedicated to such systems deployed at high-frequency bands. Due to the inherent channel sparsity, we use the power iteration and eigen-deflation methods to compute the significant eigenpairs in an on-demand manner. The in-place memory design allows the input and intermediate matrices to share the same storage, leading to reduced area. Additionally, the interleaved blockwise processing (IBP) reduces the area-latency product of the eigen-deflation engine by 41%. Experiments on real 60-GHz channel measurements validate the effectiveness of the proposed eigenpair solver. Fabricated in a 28-nm CMOS technology, the 0.8-mm2 chip consumes 39.2 mW at 240 MHz and supports matrix sizes up to 256×256. In the sparsity-aware application, it achieves a 1.91× improvement in the effective throughput compared to the state-of-the-art design.
This paper proposes a 12-bit 625-MS/s two-step pipelined-SAR ADC incorporating a self-adaptive common-mode (CM) capacitor multiplier (SACM-CM). The SACM-CM dynamically adjusts the effective CM compensation capacitance in response to output CM voltage fluctuations, enabling autonomous regulation against process, voltage, and temperature (PVT) variations without external control logic. It synergizes with a novel CM feedback (CMFB) circuit (eliminating additional loading) and a tail-less dual-inverter amplifier (DIA) in the first stage to stabilize CM and enhance linearity. Combined with the bandwidth-switching (BWS) technique, the amplifier dynamically tunes its effective bandwidth, mitigates noise, and enhances settling accuracy. Fabricated in 28-nm CMOS, the prototype achieves a Nyquist input signal-to-noise-and-distortion ratio (SNDR) of 62.25 dB, a spurious-free dynamic range (SFDR) of 78.8 dB, and a power consumption of 7.4 mW at 625 MS/s.
