We have fabricated very thin TiO 2 film (T eq ∼20Å) by RTP oxidation of sputtered Ti in NO ambient on nitrogen passivated Si substrates. The leakage current is about two orders magnitude lower than SiO 2 of identical T eq . Results show that NO passivation layer prior to sputtering is critical in reducing the leakage current. XPS results show that the temperature RTP NO oxidation of sputtered Ti is very important for achieving high quality TiO 2 films. high oxidation temperature an SiO 2 layer is formed at the interface between TiO 2 and Si and the leakage current is approaching to that of SiO 2 .

In this paper, ultra thin CVD Ta 2 O 5 stacked gate dielectrics (Teq∼14Å-22Å) was fabricated by in-situ RTP processing. The leakage current of Ta 2 O 5 devices is 10 3 × lower leakage current compared to SiO 2 of identical thickness for devices with Teq between 18Å-22Å. While Teq<18Å, the leakage current follows same train and J∼10 −3 A/cm 2 for Ta 2 O 5 stacked gate dielectrics with Teq=14Å. Superior interface properties and reliability have been obtained.

The effect of device fabrication temperature on the work function of ruthenium (Ru) metal gate and its bilayers was investigated. The work function shows strong temperature dependence when Ru electrodes are deposited on silicon oxide, SiO2, but not on hafnium silicates (HfSiOx). Specifically, the work function of Ru on SiO2 increased from 4.5 eV at 500 degrees C to 5.0 eV at 700 degrees C. On further annealing to 900 degrees C or higher, the work function dropped to about 4.4 eV. In the case of HfSiOx, the work function of Ru changed by less than 100 mV over the same temperature range. Identical temperature dependence was observed using hafnium (Hf)/Ru and tantalum (Ta)/Ru bilayers. However, the peak values of the work function decreased with increasing Hf/Ru and Ta/Ru thickness ratios. Materials analysis suggests that these trends are driven by interactions at the Ru metal gate-dielectric interface. (c) 2006 Elsevier B.V. All rights reserved.

Metal gate work function enhancement using thin AlNx interfacial layers has been evaluated. It was found that band edge effective work functions (∼5.10eV) can be achieved on hafnium-based high dielectric constant (high-k) materials using the AlNx interfacial layer and TiSiN electrodes. It was also found that the effective work function enhancement by the AlNx interfacial layer increased when the concentration of SiO2 in the gate dielectric was increased. Thus, the enhancement was minimal for HfO2 and maximum for SiO2. A model is proposed to explain these results and a bonding analysis is presented to support the proposed model.

The impact of thin metal nitride layers on the effective work function (EWF) of poly-Si/metal gate stacks has been investigated. The electrode stacks studied include very thin (0.5-2.0 nm) TaN x and MoN x metal layers sandwiched between the poly-Si gate and the gate dielectric. Both n and p-type polysilicon electrodes were evaluated. The results indicate that when the metal nitride layers are as thin as 0.5 nm, they can have significant effect on the polysilicon effective work function. The observed results are explained by reactions between poly-Si and the metal nitrides leading to the formation of Ta x Si y N z in the case of TaNx inter-layers. As the metal nitride inter-layers become thicker, the work function is controlled by the metal nitride EWF. Preliminary quasi-static C-V analysis shows minimal poly depletion with the metal inter-layers. Gate leakage current and fixed charges comparable to conventional polysilicon electrodes were obtained.

The impact of thin TaN layers (0.5–10nm) on the effective work function of polycrystalline silicon (poly-Si)∕TaN stacks has been investigated. It is found that when the TaN layer is as thin as 0.5nm, it can have a significant effect on the effective work function of poly-Si, and that n-type and p-type poly-Si behave differently. The observed results are explained by reactions between poly-Si and the TaN layer leading to the formation of TaxSiyNz at the poly-Si-gate dielectric interface. Electrical tests show minimal poly-Si depletion with the TaN layers, and gate leakage current and fixed charges that are comparable to conventional poly-Si electrodes. The results show that these stacked electrodes can be useful for nearly n-type effective work functions (4.2–4.3eV).

In Recent results suggested that doping with a small amount of using standard ceramic processing techniques can increase the dielectric constant of significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped films are deposited using , $C_8H_{24}N_4Ti$, and on both Si and -nitrided Si substrates. An -based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the dielectric. XPS analyses confirm the formation of a ( composite oxide. A high quality gate stack with EOT (Equivalent Oxide Thickness) of and leakage current @ Vg=-1.0V has been achieved. We have also succeeded in forming a composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD , suggesting that the dielectric constant of is not affected by the addition of .

The materials and processing challenges for the fabrication of high quality, ultra-thin CVD high-K gate stack are reviewed along with the most recent results on CVD ZrO/sub 2/, HfO/sub 2/ and their silicates. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest equivalent oxide thickness (EOT) is discussed. Results are presented on thermal stability of high-K materials, and interfacial reactions of high-K/Si and highK/gate electrode. We also discuss key factors that govern the conduction and degradation mechanisms in high-K gate stack. Both poly-Si and poly-SiGe are explored as possible gate electrode materials and the upper thermal budget limit for such materials is discussed.

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

MOSFETs with high quality ultra thin (EOT/spl sim/10.3 /spl Aring/) HfO/sub 2/ gate stacks and self-aligned dual poly-Si gate are fabricated and characterized. Both n- and p-MOSFETs show good electron and hole mobility, respectively, and excellent sub-threshold swings. In addition, the HfO/sub 2/ gate stack exhibits excellent thermal stability with poly-Si gates up to 1050/spl deg/C/30 s gate activation annealing and shows excellent TDDB reliability characteristics with negligible charge trapping and SILC under high-field stressing.

In this paper, we have successfully fabricated and characterized self-aligned TaN and TaN/poly-Si gated n-MOSFETs with ultra thin (EOT=11 /spl Aring/) CVD ZrO/sub 2/ gate dielectrics. It is show that while both gate stacks show excellent leakage current and good thermal stability after a 900/spl deg/C, 30 s, N/sub 2/ anneal, the TaN/poly-Si ZrO/sub 2/ devices exhibit superior thermal stability even after 1000/spl deg/C, 30 s, N/sub 2/ anneal. In addition, the TaN/poly-Si devices show negligible frequency dependence of CV, charge trapping, and superior TDDB characteristics, compared to TaN devices. Well-behaved N-MOSFETs with both TaN and TaN/poly-Si gate electrodes are demonstrated.

P-MOSFETs with 14 /spl Aring/ equivalent oxide thickness (EOT) were fabricated using both JVD Si/sub 3/N/sub 4/ and RTCVD Si/sub 3/N/sub 4//SiO/sub x/N/sub y/ gate dielectric technologies. With gate length down to 80 nm, the two technologies produced very similar device performances, such as drive current and gate tunneling current. The low gate leakage current, good device characteristics and compatibility with conventional CMOS processing technology make both nitride gate dielectrics attractive candidates for post-SiO/sub 2/ scaling. The fact that two significantly different technologies produced identical results suggests that the process window should be quite large.

The rutile stoichiometric phase of RuO2, deposited via reactive sputtering, was evaluated as a gate electrode on chemical vapor deposited ZrO2 and Zr silicate for Si–p-type metal–oxide–semiconductor (PMOS) devices. Thermal and chemical stability of the electrodes was studied at annealing temperatures of 400, 600, and 800 °C in N2. X-ray diffraction was measured to study grain structure and interface reactions. The resistivity of RuO2 films was 65.0 μΩ cm after 800 °C annealing. Electrical properties were evaluated on MOS capacitors, which indicated that the work function of RuO2 was ∼5.1 eV, compatible with PMOS devices. Post-RuO2 gate annealing up to 800 °C, resulted in only a 1.4 Å equivalent oxide thickness (Tox-eq) change and 0.2 V flatband voltage change for Zr silicate and a 4 Å Tox-eq change for ZrO2 dielectrics. Tantalum electrodes were also studied on ZrO2 as a comparison of the stability of RuO2 electrodes.

In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO/sub 2/. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed.

Mo metal gate p-MOSFETs with several advanced gate dielectrics were fabricated. A suitable p-MOSFET work function was achieved and good device characteristics were obtained in all cases. Thermodynamic stability of Mo on Si/sub 3/N/sub 4/, ZrO/sub 2/ and ZrSiO/sub 4/ was verified by good carrier mobility agreement with the universal mobility model.

We have developed and demonstrated an in-situ rapid thermal CVD (RTCVD) process for the fabrication of high quality ultra thin CVD HfO/sub 2/ gate stack that is compatible with conventional self-aligned poly-Si gate technology. These poly-Si gated HfO/sub 2/ gate stack show excellent interface properties, EOT=10.4 /spl Aring/, and leakage current Jg=0.23 mA/cm/sup 2/ @Vg=-1 V which is several orders of magnitude lower than RTO SiO/sub 2/ with poly-Si gate. In addition, the HfO/sub 2/ gate stack is thermally stable in direct contact with n/sup +/-poly Si gate under typical dopant activation conditions. These films also show excellent reliability under high-field electrical stress. We have also fabricated and demonstrated NMOSFETs, and studied boron penetration in HfO/sub 2/ gate stack with p/sup +/-poly Si gate.

A novel technique - N-2 ion implant (N-2 III) followed by vertical high pressure (VHP) O-2 re-oxidation in a furnace, capable of growing oxides of multiple thickness is presented. It is observed that the oxidation rate can be well modulated by varying the N-2 I/I dose, and VHP O-2 re-oxidation provides enhanced oxide growth rate and controls the nitrogen profile in the film, as compared to RTO or furnace O-2 re-oxidation. Therefore, more than 500% differential oxide growth rate can be realized by using N-2 I/I (1x10(14) - 3x10(15) cm(-2)) and VHP O-2 re-oxidation (15-25atm, 750-875 degreesC). In addition, post-implant RTA N-2 anneal is found to improve the channel carrier mobility ((mu (eff)), and alter the flat-band (V-FB) and threshold voltages (V-T) without increasing the oxide thickness.

Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.