This paper describes a design integration method that simulates the sensing characteristics of a low-input-impedance sensing circuit combined with a sensor having a complexly structured vibration amplification mechanism (VAM). The sensing circuit that detects vibrations with zero power transforms acceleration to an electrical signal by transferring charges by utilizing the kinetic energy of the movable element in the sensor. The VAM adjusts the resonance frequency to within the target range of the vibration spectrum to obtain a sufficient signal intensity. For the circuit evaluation, a vibration sensor needs to be connected to a test chip because the input impedance is set low to improve charge transfer efficiency and the voltage signal generated by the charge transfer is affected by the vibration waveform. In addition, the VAM has a complex structure that is not regarded as a single rigid body, making it difficult to estimate the sensing performance. The proposed method solves this problem by simplifying the VAM simulation model using two parameters of the spring elements and extracting the parameters from a measured data point based on an independent relationship between the parameters. A test chip fabricated by using the 0.35-µm CMOS process detects a vibration at 40 Hz and 0.4 g with 0.7 nW, and the validity of the proposed method is confirmed via the consistency between the simulated results obtained based on the extracted parameters and the entire set of measured data. The design integration makes it possible to design sensing circuits that need the complex-structured sensor to be connected for evaluation.

A new threshold circuit technique is proposed for a vibration sensing circuit that operates at a nanowatt power level. The sensing circuits that use sample-and-hold require a clock signal, and they consume power to generate a signal. In the use of a Schmitt trigger circuit that does not use a clock signal, a sink current flows when thresholding the analog signal output. The requirements for millimeter-sized wireless sensor nodes are an average power on the order of a nanowatt and a signal transition time of less than 1 ms. To meet these requirements, our circuit limits the sink current with a nanoampere-level current source. The chattering caused by current limiting is suppressed by feeding back the change in output voltage to the limiting current. The increase in the signal transition time that is caused by current limiting is reduced by accelerating the discharge of the load capacitance. For a test chip fabricated in the 0.35-mu m CMOS process, the proposed threshold circuits operate without chattering and the average powers are 0.7-3 nW. The signal transition times are estimated in a circuit simulation to be 65-97 mu s. The proposed circuit has 1/150th the power-delay product with no time interval of the sensing operation under the condition that the time interval is 1s. These results indicate that, the proposed threshold circuits are suitable for vibration sensing in millimeter-sized wireless sensor nodes.

The requirements of low power integrated circuits are very important in all electronic portable equipment's. Normally SRAM consume more power during read and write operations because of more power consumptions speed of the circuit will be reduced finally the performance will be degraded. To reduce power consumption and increase RNM (Read Noise Margin) the adiabatic change of word line voltage is used in single bit line SRAM and also sense amplifier flip flop and pre-charge circuit is used. During read operation pre-charge circuit is connected with selective bit lines to minimize the overall RAM power consumption and sense amplifier flip-flop is used to increase the speed of the operation. Using of adiabatic circuit in

The requirements of low power integrated circuits are very important in all electronic portable equipment's. Normally SRAM consume more power during read and write operations because of more power consumptions speed of the circuit will be reduced finally the performance will be degraded. To reduce power consumption and increase RNM (Read Noise Margin) the adiabatic change of word line voltage is used in single bit line SRAM and also sense amplifier flip flop and pre-charge circuit is used. During read operation pre-charge circuit is connected with selective bit lines to minimize the overall RAM power consumption and sense amplifier flip-flop is used to increase the speed of the operation. Using of adiabatic circuit in

Long-distance transmission of high-quality and high-power laser optics has been achieved for the first time in the world by combining the advanced optical fiber and optical device technologies developed by NTT in the optical communications field with the high-power laser processing technology of Mitsubishi Heavy Industries, Ltd.The use of laser processing technology is spreading rapidly at manufacturing sites in the automobile, aircraft, and other industries.The results of this joint research are expected to be the first step in revolutionizing the concept of manufacturing for a variety of social infrastructures through B2B2X (business-to-business-to-X) initiatives.

A programmable voltage detector (PVD) for battery management is proposed to achieve the programmability of the detection voltage ( $V_{\mathrm {DETECT}}$ ). Thanks to the programmability, users can set an appropriate $V_{\mathrm {DETECT}}$ for battery management considering the operating voltage of the battery. For batteries including Li-ion and NiMH batteries, a PVD is required to achieve wide programmed $V_{\mathrm {DETECT}}$ range from 1.0 to 4.35 V with a fine voltage step of ±42 mV. Furthermore, the power consumption of the PVD must be minimized since the PVD is always operating in battery management. To achieve both the target programmability of $V_{\mathrm {DETECT}}$ and the low power consumption of the PVD, a programmable voltage reference (PVREF) using a fine voltage-step subtraction (FVS) method is proposed. The FVS is a combination of fine and coarse programming for the output of the PVREF, which achieves a fine voltage step and a wide programmable range of $V_{\mathrm {DETECT}}$ achieving both a low temperature coefficient of $V_{\mathrm {DETECT}}$ and low power consumption of the PVD. The measurement results of the PVD fabricated in a 250-nm CMOS process show a current consumption of the PVD of 1.2 nA at 3.5 V and a temperature coefficient of $V_{\mathrm {DETECT}}$ of 0.28 mV/°C. The PVD enables the widest programmable range of $V_{\mathrm {DETECT}}$ from 0.90 to 4.39 V, fine $V_{\mathrm {DETECT}}$ resolution of ±31.5 mV, and 56-level linear, monotonic programmability of $V_{\mathrm {DETECT}}$ .

The requirements of low power integrated circuits are very important in all electronic portable equipment's. Normally SRAM consume more power during read and write operations because of more power consumptions speed of the circuit will be reduced finally the performance will be degraded. To reduce power consumption and increase RNM (Read Noise Margin) the adiabatic change of word line voltage is used in single bit line SRAM and also sense amplifier flip flop and pre-charge circuit is used. During read operation pre-charge circuit is connected with selective bit lines to minimize the overall RAM power consumption and sense amplifier flip-flop is used to increase the speed of the operation. Using of adiabatic circuit in

This paper presents an ultra-low power and temperature-independent voltage detector with a post-fabrication programming method, and presents a theoretical analysis and measurement results. The voltage detector is composed of a programmable voltage detector and a glitch-free voltage detector to realize both programmable and glitch-free operation. The programmable voltage detector enables the programmable detection voltages in the range from 0.52V to 0.85V in steps of less than 49mV. The glitch-free voltage detector enables glitch-free operation when the supply voltage is near 0V. A multiple voltage copier (MVC) in the programmable voltage detector is newly proposed to eliminate the tradeoff between the temperature dependence and power consumption. The design consideration and a theoretical analysis of the MVC are introduced to clarify the relationship between the current in the MVC and the accuracy of the duplication. From the analysis, the tradeoff between the duplication error and the current of MVC is introduced. The proposed voltage detector is fabricated in a 250 nm CMOS process. The measurement results show that the power consumption is 248pW and the temperature coefficient is 0.11mV/degrees C.

A systematic design method is considered for maximizing the sensitivity of electrooptic sensors used for electric-field detection. The design method can be reduced to a routine procedure that includes matrix manipulation and differentiation. By applying the design method, the maximum sensitivity is realized with fewer optical components than in conventional electrooptic sensing systems. Since the proposed method shows a wide generality, it can be applied to designing sensors including various optical crystals.

In magnetic-resonance wireless power transfer systems, a transmitter is equipped with a floating coil. We investigated the functions of the floating coil by analyzing an equivalent-circuit model of the transmitter. It is derived from the model that currents of the floating coil can be amplified without increasing the power consumption of the transmitter. As a result, strong magnetic fields can efficiently be generated with the floating coil. By solving the model, we obtain formulas for maximizing magnetic-field amplitude at an arbitrary frequency. The validity of our analysis is experimentally demonstrated.

The purpose of this study was to improve the optical characteristics of garnet ferrite films sputter-deposited on a glass substrate. The magnetooptical properties of the garnet ferrite film are strongly influenced by the thermal stress imposed on the substrate during crystallization. The condition of the interface between the garnet film and the substrate during the initial film deposition affects the magnetooptical characteristics of the entire film. In particular, we revealed the effect of stress generated at the interface on the crystallinity of the deposited garnet films with a stress relaxation buffer layer by observing the film cross section and the film surface. In addition, we qualitatively estimated of the effect of cracking in the garnet film on a glass substrate.

We investigated the amplification of the magnetic field generated by a floating coil placed in resonance with a driving coil connected to a signal source. With this method, the magnetic field can be amplified without increasing power consumption of the signal source. From an equivalent-circuit model composed of the floating and driving coils, we derived useful formulae for maximizing the magnetic-field amplitude at an arbitrary target frequency. The validity of the formulae was experimentally demonstrated. It was found that under specific conditions, the current induced in the floating coil can be increased by more than one order of magnitude compared to the current in the driving coil, leading to amplification of the magnetic field that reaches 22 dB at the target frequency of 10 MHz without increasing power consumption. We also found that the floating coil is effective in suppressing undesirable magnetic field components originating from common-mode currents. These results pave the way to further reduction of the power consumption in wireless communication schemes such as near field communication.

A programmable voltage detector (PVD) for the battery management is developed for the first time. In battery management applications, PVD's with fine voltage resolution (<+/- 1% of battery voltage) are required to precisely control the charging and discharging of the battery and to provide a universal voltage detector. The proposed fine voltage-step subtraction (FVS) method in PVD enables the wide detection voltage (V-DETECT) range from 1.88V to 4.67V, fine V-DETECT resolution of 50mV, and the 56-level linear programmability. Compared with previous publications, the 50-mV resolution is the smallest and the 56-level programmability is the largest. The programmability of V-DETECT enables a V-DETECT hopping capability achieving time-varying V-DETECT to reduce the number of voltage detectors in the battery management system. PVD fabricated in 5V, 250-nm CMOS process shows the measured power consumption of 13nW at 3.5V and the temperature coefficient of 0.17mV/degrees C in -20 degrees C to 80 degrees C.

Analytical theory and simulation-based analysis for optimizing sensitivity of RF energy harvester are discussed. A target harvester is a widely-used MOSFET Dickson charge-pump harvester from a small-signal RF power with a voltage booster at the front end. Charging time is also analyzed. Derived expressions show good match with simulation results. The results provide an insight for design optimization based on circuit and device parameters.

The Internet of Things (IoT) is opening the doors to many new devices and applications. Such an increase in the variety of applications requires reconfigurable, flexible and expandable hardware for fabrication and development cost reduction. This has been achieved for the digital part with devices like Arduino. However, the sensor readout Analog-Front-End (AFE) circuits are mainly designed for a specific sensor type or application. Such an approach would be feasible for the current small number of applications and sensors used. However, it will increase cost drastically as the variety and number of applications and sensors are increased. Moreover, flexibility and expandability of the system will be limited. Therefore, a universal sensor platform that can be reconfigured to adapt to various sensors and applications is needed. Moreover, an array of such circuit can be made with the same sensor to increase measurement accuracy and reliability. It can also be used to integrate heterogeneous sensors for increasing the flexibility of the system, which will make the system adaptable to many applications through only activating the desired sensors. In this paper, an 8-mode reconfigurable sensor readout AFE with offset-cancellation-resolution enhancing scheme is proposed to serve as a step towards a universal sensor interface. The proposed AFE can be reconfigured to interface resistive, capacitive, current producing, and voltage producing sensors through direct or capacitive connection to its terminals. The proposed system is fabricated in 180nm CMOS process and has successfully measured the four types of sensor outputs. It has also been interfaced to Arduino board to allow easy interfacing of various sensors. Therefore, the proposed work can be used as general purpose AFE resulting in manufacturing and development cost reduction and increased flexibility and expandability.

A Wide Frequency PLL-less Clock Generator with Fast Intermittent Operation is presented in this paper to replace both the external frequency reference and PLL combination used in current wearable medical devices. The system uses one loop to stabilize the amplitude and the other to stabilize the slope of a saw-tooth signal to generate stable frequency over a wide range. Measurement results from a chip fabricated in 180nm CMOS process gives a linear frequency range of 0.1MHz-10MHz and 7us settling time without using a PLL. The total power consumption is 360uW that includes output buffers and external current sources with ±0.84% variation in frequency from 0-70 degrees. Using the proposed system as a clock generator for microcontrollers used in current wearable medical devices, would result in a one or more order of magnitude reduction in power consumption.