In this letter, a thermal conduction measurement method for thermal radiation sensors, such as vacuum-packaged bolometers, is presented. The idea of the method is deduced from the classical 3.-method proposed by Cahill [1]. Here, the measurement geometry is a complete sensor geometry, which is suspended from the substrate by thermal isolation legs. The most relevant performance factor for such a sensor is the thermal isolation; this is why the thermal conduction measurement is so important to design better sensors. Additionally, the thermal loss mechanisms need to be investigated because the sensors are normally operated at the thermal radiation limit. Therefore, these loss mechanisms are modeled with an electrothermal equivalent circuit of the whole measurement setup. The measurement method is then used to measure and derive the thermal conduction of known single microbolometer structures.

This study reports on the development of vertical, partially encapsulated nanoelectrodes for electrically contacting the interior of electrogenic cells with microelectronics. Intracellular electrical stimulation and recording with single cell resolution enables new insights into the electrophysiology of cells embedded in a complex multicellular network, providing detailed understanding of fundamental processes affecting cell to cell communication and thereby paving the way for novel applications including pharmacological studies and other neuromodulation techniques like focused ultrasound and electroceuticals. In order to minimize the influence of the measurement system, an approach based on nano-sized hollow electrodes, achieving an adhesion based intracellular access, is used. The focus of the presented work is on the novel fabrication technology and the characterization of the resulting nanoelectrodes. In CMOS compatible processes, the hollow geometry is achieved using a sacrificial layer technique combining deep reactive ion etching and atomic layer deposition of Ru. For decoupling the extracellular milieu, a partial passivation of the nanoelectrodes by Ta2O5 is realized. The monolithic integration allows an application specific fine-tuning of geometry and placement of the nanoelectrodes. A discrete microelectrode array was designed to electrically and electrochemically characterize the nanoelectrodes. Resistance measurements, cyclic voltammetry and electrochemical impedance spectroscopy show the feasibility of the developed electrodes as an electronic interface to electrochemical fluids. Specifically, an electrode resistance of 2.92 k Omega and charge delivery capacitance of 748.13 mu C/cm(2) were observed. Confocal microscopy analyses of neural cells interfaced with the nanoelectrodes indicate an adhesion based intracellular access as well as biostability and biocompatibility. [2020-0224]

In this work, ALD films are developed by alternately applying semiconducting ZnO grains and dielectric Al2O3 grains which result in homogeneous composites with humidity-sensitive properties. Various films, which differ in the grain size ratio of ZnO to Al2O3, are tested with 2D sensor structures. IV-t measurements during interaction of the films with applied water droplets reveal current and resistance changes of up to five orders of magnitude. 3D applicability of these humidity-sensitive films is proven by cross-sectional SEM images of an all-around coated silicon chip.

As a structural layer for microelectromechanical systems, in situ doped polycrystalline silicon germanium (poly-SiGe) can be deposited directly through openings of the uppermost dielectric onto the underlying metal interconnects to achieve electronic connections to the CMOS electronics. Differently from the existing works where poly-SiGe was deposited with the low pressure chemical vapor deposition (LPCVD), the plasma enhanced chemical vapor deposition (PECVD) method to produce poly-SiGe films forming the structural layer and the electrical contacts has been deployed. Compared with the films deposited with LPCVD, the as-deposited PECVD films formed contacts yielding low resistivity without any extra processing, such as precleaning and annealing. To investigate the contact resistance of poly-SiGe and polycrystalline germanium (poly-Ge) on titanium, Kelvin structures were fabricated and characterized. The substrate temperatures during the deposition were as low as 375°C for poly-SiGe and 340°C for poly-Ge, and low specific contact resistances of 3.2 × 10−6 Ω cm2 and 8.0 × 10−6 Ω cm2 respectively. This is expected to arise from the additionally acquired activation energies of ions from the plasma during PECVD. It is possibly due to the additional energies from the plasma, a titanium germanosilicide interfacial layer between poly-SiGe (or poly-Ge) and titanium (Ti) can be generated without high temperature processes. A metal stack was employed, to ensure a good adhesion, to block the diffusion and serve as an anti-reflection layer at the lithography.

In this work, a concept and proof of principle regarding a fabrication technique for vertical nanoelectrodes is presented. CMOS-compatible processes for the fabrication of three-dimensional tubes which are partly encapsulated by an insulation layer are conceived. An extended sacrificial layer technique using deep reactive ion etching (DRIE) and atomic layer deposition (ALD) of encapsulation and electrode material was developed. Additional spacing techniques for tapering of electrode diameter and tip post-lithographically are investigated. Finally, free-standing nanoelectrodes and test structures were produced. The resulting tunable nanoelectrode array can lead to a novel device for a bidirectional interface between integrated circuits and living cells.

Size reduction in microelectromechanical systems (MEMS) leads to more complex behavior of physical parameters affected by quantum mechanical effects. Besides specific electrical resistance, thermal conductivity is a characteristic parameter for designing application-specific MEMS. Nanotubes are able to realize an electrical contact between a sensor element and a CMOS substrate while providing sufficient thermal isolation. A model for the prediction of thermal conductivity of nanotubes, compounded of alloys and demonstrated for titanium nitride, is presented here. The influence of the crystal structure on the mean free path is considered to limit electron and phonon mobility in thin layer geometries. A 3-D-2-D transition in the density of states of electrons and phonons is taken into account because feature sizes today are below the boundary scattering regime. We show that the dominating thermal conductance mechanism varies between phonons and electrons as a function of film thickness in TiN.

In this work, the hermeticity of diaphragm structures is investigated and optimized. The diaphragms are developed for the monolithic post-CMOS integration of capacitive pressure sensors. Si 1-X Ge X is used as diaphragm material and was deposited at temperatures below 400 °C.The hermeticity of the diaphragms was evaluated at a He pressure of 1800 hPa and in a temperature range from 50 °C to about 100 °C. The diffusion coefficients were determined by measuring the changes of diaphragm deflections due to He-diffusion inside the cavity.In the CVD process of Si 1-X Ge X cover layer on a polycrystalline p + Si 1-X Ge X diaphragm for closing the etch access holes, a variation of the SiH 4 and GeH 4 gas flows at a substrate temperature of about 380 °C was investigated regarding the selectivity of the layer growth on different surfaces (p + Si 1-X Ge X , Si, and SiO 2 ). The selectivity of the layer growth against Si and SiO 2 increases with the GeH 4 ratio in the process gas flow. With a pure GeH 4 gas flow, an optimisation of the parameters selectivity, He-diffusion and intrinsic stress of the Si 1-X Ge X cover layer was found.

In this work, super-hydrophobic coatings are investigated for drop transport with electrowetting-on-dielectric (EWOD). At first, the basics of EWOD are shown. Then the impact of decreasing the thickness of the dielectric layer and using super-hydrophobic coatings on the actuation voltage Vmin for drop transport is presented. In the last part, simulation results made with COMSOL Multiphysics ??? are shown and the results are discussed.

This paper presents the results of high-performance infrared detectors (IRFPA – InfraRed Focal Plane Array) based on uncooled microbolometers with 17 μm and 12 μm pixel pitch and a chip-scale-package as the vacuum package developed and fabricated by Fraunhofer-IMS. Like CMOS image sensor IRFPAs also have been following the trend of reducing the pixel size in order to reduce the costs and increase the optical resolution. For microbolometer based uncooled IRFPA the pixel pitch has been reduced from 35 μm pixel pitch ten years ago via 25 μm and 17 μm down to 12 μm. Fraunhofer IMS has developed digital IRFPAs featuring a direct conversion of the microbolometer’s resistance into a 16 bit value by the use of massively parallel on-chip Sigma-Delta-ADCs achieving a high scene temperature dynamic range of more than 300 K and a very low NETD-value below 50 mK. Due to a broad-band antireflection coating the digital IRFPAs achieve a high sensitivity in the LWIR (wavelength 8 μm to 14 μm) and MWIR (wavelength 3 μm to 5 μm) range. In this paper the microbolometer, the vacuum-packaging, the architecture of the readout electronics, and the electro-optical performance characterization will be presented.

An analytical model for the thin-film silicon-on-insulator pin-diode leakage current is presented. Particularly the back-gate potential influence on the leakage current is addressed. The two-dimensional Poisson equation is simplified and then solved including the influence of the back-gate potential. Subsequently the analytical model is verified by comparison with numerical simulation and measurements. For the verification of the model the dependence on the back-gate potential, reverse voltage, device geometry, doping concentration and polarity is considered. In this procedure the interface recombination velocity is used as fitting parameter. The model verification shows an accurate modeling of the leakage current at full depletion in combination with a back-gate potential dependence. The usage of the model is limited to back-gate and reverse potentials close to full depletion state of the pin-diode. (C) 2017 Elsevier Ltd. All rights reserved.

Fraunhofer IMS develops and fabricates far-infrared focal plane arrays (IRFPA) using microbolometers with a pixel pitch of 17μm technology realized on top of a 0.35 μm CMOS readout integrated circuit (ROIC). The microbolometers are encapsulated by a Chip-Scale-Package (CSP) to ensure a high quality vacuum level. The CSP is realized by placing an infrared transparent lid above a solder frame surrounding the microbolometer array. To concept a wafer-level test it is very challenging to implement highly accurate electrical stimuli and a far infrared radiation source (black body) while affecting the wafer-prober handling by a non-flat wafer surface, due to the infrared transparent lids of the CSP. Accordingly, wafer-level test has been developed based on a PC which controls, by using a test program, the wafer handling of a prober, the electrical stimuli of a test hardware, and the far-infrared radiation such as the optical stimuli. Thus, the most important electro-optical parameters of IRFPAs will be measured at wafer-level: Noise Equivalent Temperature Difference (NETD), responsivity, and the percentage of the defective pixels.

Zusammenfassung In diesem Paper wird ein innovatives Konzept zur Herstellung von hochempfindlichen ungekühlten Mikrobolometern, zur Detektion von langwelliger Infrarotstrahlung (IR-Strahlung) in einem Wellenlängenbereich von 8 μm–14 μm, beschrieben. Der Ansatz basiert auf der Realisierung der thermischen Isolierung und gleichzeitiger elektrischer Kontaktierung der Mikrobolometer mit Hilfe von ausreichend langen und dünnbeschichteten Hohlröhrchen (hier als Nanotubes bezeichnet), welche mit Technologien und Prozessen aus der Mikrosystemtechnik hergestellt werden können. Somit wird der relative Flächenanteil des Absorbers bei einer gegebenen Pixelgröße maximiert, da laterale Stege, welche bislang Hauptbestandteil der thermischen Isolierung waren, komplett entfallen. Der resultierende thermische Leitwert kann über die einzelnen Schichtdicken, Grundradius und Länge der Nanotubes flexibel und unabhängig von der Pixelgröße eingestellt werden. Die gefertigten Nanotube-Mikrobolometer werden zunächst anhand von Teststrukturen im Hinblick auf die elektro-optischen und mechanischen Eigenschaften grundlegend charakterisiert. Der Fokus liegt in dieser Arbeit auf Pixelgrößen von 12 μm.

Physically Unclonable Functions (PUFs) offer enticing possibilities to incorporate hardware-based security on semiconductor device level. In order to make efficient use of PUF functionality in lightweight cryptographic applications, a low-overhead implementation in terms of chip area and power consumption is required. In this paper a fully differential readout circuit is proposed that allows the generation of multiple bits from selected pairs of PUF-elements. The IC-design and working principle are explained on basis of a critically-sized nMOS transistor array serving as a PUF-primitive. First results obtained from circuit simulations and wafer-level measurements of 30 PUF-instances fabricated in a 0.35 μm CMOS technology are presented. Evaluation of the intraand inter-Hamming distance with average values of 9.42% and 49.46%, respectively, shows that device identification based on the extracted keys is feasible. In order to increase the number of unique keys obtainable for each PUF-instance layout improvements in form of additional row select connections are proposed.

In this paper a novel concept for the fabrication of highly sensitive uncooled microbolometers is presented. The approach is based on the realization of thermal isolation and simultaneous electrical contacting of the microbolometers by means of sufficiently long and thin coated nanotubes, which can be fabricated by post processing on top of CMOS wafers comprising the ROIC. Thus, the effective area of the absorption layer is maximized at a given pixel size, as lateral legs, which have been the main component of the thermal isolation commonly, are completely omitted. The resulting thermal conductance can be tuned independently from the pixel size by varying the geometry and structuring of the nanotubes. Based on test structures the nanotube microbolometers are characterized with respect to electro-optical and mechanical properties. The focus in this paper is on nanotube microbolometers with a pixel size of 12 mu m.

We report on a study of enzymatic glucose and lactate sensors for measurements of wide concentration ranges from 1 mM up to 600 mM and 900 mM, respectively, in biotechnological processes. Diffusion limiting polyurethane membranes were used to extend the linear measurement range and the influence of two fabrication parameters on membrane properties and sensor performance evaluated. The polymer concentration was varied between 4% and 10% and the ratio of the solvents tetrahydrofuran and dimethylformamide between 9:1 and 1:9. Surface morphology and permeability of the membranes and the linear measurement range of membrane-covered enzyme sensors were determined. A distinct relationship between the different results was found. The sensors retained their functionality after being sterilized using gamma and electron beam irradiation. The long-term performance of the sensors was evaluated and good performance in the glucose monitoring of a culture of Saccharomyces cerevisiae over 13 days was shown. (C) 2016 Elsevier B.V. All rights reserved.

Within the framework of the scientific project MINAPSO (Mikrochip Navigierte Parallel Sortieranlage), a device has been developed that is intended to separate specific biological cells out of heterogeneous cell suspensions on chip level. The process relies on parallel splitting of cell containing droplets, accomplished by the effect of electrowetting and recognition of fluorescently labelled cells. We present an automatic cell sorting platform consisting of a silicon based electrowetting chip and a fluorescence microscope. Based on the device, all relevant fluid operations like drop extraction, drop transport and drop splitting were verified by parameter variations. Measurements of particle distributions support the technical feasibility of the sorting concept and the proof of principle is conducted by a complete sorting experiment.

In this article a model is introduced that describes the charge transfer in pixels of an image sensor. The model is suitable for image sensors where lateral drift field photo detectors were implemented and considers the effects of thermal diffusion, drift due to the built-in potential gradient, and self-induced drift.The analytical result is compared with a numerical solution and confirmed by measurements. With this model it is possible to predict the amount of collected charge at the sense node for very short integration times in comparatively long pixel structures. This is particularly important for indirect time-of-flight applications with CMOS image sensors.This approach enables the optimization of the pixel layout as well as an advanced calibration that might possibly enhance the distance precision. The model can also be applied to image sensors featuring pinned photodiodes. (C) 2016 Elsevier Ltd. All rights reserved.

We investigated the leakage current of thin film silicon-on-insulator (SOI) pin-diodes in dependence of the back-gate potential and hot carrier induced traps. Leakage current of virgin and hot-carrier stressed diodes was measured at distinct back-gate potentials. TCAD simulations were used to determine the mechanisms of leakage current generation at specific back-gate potentials. Traps were introduced to study the impact of hot-carrier stress on the leakage current. Location, polarity and density of traps were considered. For a virgin device tunneling is predominant in inversion and accumulation. In full depletion surface generation dominates the leakage behavior. Surface and oxide traps shift the leakage current and alter its mechanism with increasing density, i.e. stress time. In inversion trap generation dominates at the top SOI interface. In depletion top and bottom interface traps are generated.

We report on an electrochemical measurement setup comprising a glucose sensor and a CMOS potentiostat with a two-layer membrane as the first steps toward the development of an integrated in-situ sensor system for bioreactors. The potentiostat has a chip size of 2.1 mm × 2.5 mm and a linear current range from -220 nA to 240 nA with a linearity of R2 = 0.9995. For wide range measurements of glucose concentrations in cell culture media, electrodes functionalized with the enzyme glucose oxidase were spin-coated with membranes made from polydimethylsiloxane (PDMS). A two-stage curing scheme of the PDMS was applied, and different membrane thicknesses and curing times were evaluated. With these membranes, glucose concentrations up to 500 mM were measured with a linear measurement range up to 200 mM. The sensors were successfully employed in the glucose monitoring of a culture of Saccharomyces cerevisiae to monitor the glucose consumption of the cells. For interference elimination, the cellulose acetate membranes were employed.