The hybrid modular multilevel converter (Hybrid-MMC) integrates half-bridge and full-bridge sub-modules (HBSMs and FBSMs) to improve operational flexibility in high voltage direct current (HVDC) applications. Owing to this hybrid configuration, the converter can withstand wide DC-side (DCS) voltage variations, ranging from nominal levels to DC short-circuit fault (DC-SCF) conditions. By incorporating approximately 50% FBSMs, the Hybrid-MMC can block DC-SCFs, sustain reactive power exchange, and operate under reduced DCS voltage conditions. However, under DC-SCF conditions, excessive DCS and arm currents, along with overvoltages across FBSM capacitors, may arise. Such conditions can overstress semiconductor devices and capacitors in submodule (SM) devices and pose a risk to DCS equipment. To enhance transient fault ride-through (FRT) capability, this article proposes a hybrid modulated model predictive control ((HMPC)-P-2) strategy based on a three-phase Hybrid-MMC model (TP-(HMPC)-P-2). The proposed method reduces DCS fault current by about 12.5%, arm overcurrents by 20%, and fault clearing time by 3% compared with the per-phase (HMPC)-P-2 (PP-(HMPC)-P-2) approach. In addition, a systematic closed-loop second-harmonic circulating current injection (SCL-SHCC) method is introduced to mitigate capacitor voltage instability under overmodulation conditions. The combination of TP-(HMPC)-P-2 and SCL-SHCC ensures stable converter operation even under severe overmodulation, using only 25% of the FBSMs. The effectiveness of the proposed control methods is validated through comprehensive MATLAB/Simulink simulations. Furthermore, experimental tests are conducted on a five-level Hybrid-MMC prototype implemented on a ZYNQ-based hardware platform.

DC fault is one of the critical issues in modular multilevel converter (MMC)-based high voltage DC (HVDC) systems. Existing DC fault detection schemes suffer from several limitations, including poor sensitivity to high-resistance faults, low noise immunity, high sampling-frequency requirements, and significant computational burden. To address these limitations, this paper proposes a novel wavelet function derived from the transient characteristics of fault currents in MMC-based HVDC systems to optimize the performance of the wavelet transform for DC fault detection. This work rigorously presents the mathematical equations describing the parameters of the proposed transient fault current-based wavelet function, and a systematic, step-by-step design procedure is comprehensively explained. Furthermore, a performance index, termed the similarity factor, is introduced to evaluate the performance of the proposed wavelet compared to conventional alternatives. Based on the proposed wavelet function, a novel DC fault detection scheme is developed, providing enhanced noise immunity compared with the conventional methods. In addition, unlike conventional approaches, the proposed scheme exhibits high capability to detect high-resistance DC faults up to 2.5 p.u. while substantially lowering both computational time and sampling-frequency requirements. The effectiveness of the proposed scheme is validated through real-time simulations and experiments on a scaled-down prototype.

This work investigates a hybrid converter for ultra-fast charging of heavy-duty electric vehicles (EVs). The system combines a medium-voltage modular multilevel converter (MMC) with an active-bridge stage and employs a quasi-two-level (Q2L) modulation scheme. The converter directly interfaces an MV-DC grid with an 800 V battery bus, taking advantage of the MMC modularity and scalability while providing galvanic isolation through a medium-frequency transformer. By using Q2L modulation on the MMC AC side, the design achieves controllable voltage slew rates and reduces stress on the transformer, thereby extending its lifetime. Performance is evaluated through detailed simulations, including step changes in load and current references under constant-voltage (CV) and constant-current (CC) charging modes, with analysis of the converter’s dynamic response during transients. A complete battery charging profile from 20% to 100% state of charge is also simulated, featuring a 500 A CC phase followed by a 700 V CV phase. The results demonstrate reliable operation, good dynamic performance, and a smooth transition from CC to CV, confirming the feasibility of the proposed configuration for high-power EV fast-charging applications.

This article proposes a method for capacitor voltage balancing in hybrid modular multilevel converters (hybrid MMCs) under conditions of reduced dc-link voltage and unbalanced grid operation. Hybrid MMCs employ both half-bridge submodules (HBSMs) and full-bridge submodules (FBSMs), which can lead to capacitor voltage imbalances when subjected to such disturbances. To address this issue, the article first analyzes the operating principles and energy exchange mechanisms between the two submodule types. Then, it introduces a control strategy based on negative-sequence reactive current (NSRC) injection to effectively maintain capacitor voltage balance under such conditions. The amplitude of the injected NSRC is calculated, and its influence on the capacitor voltage of HBSMs and FBSMs is explored. Finally, MATLAB/Simulink simulations and experimental validation on a scaled-down prototype confirm that the proposed NSRC injection strategy effectively balances the capacitor voltages between the HBSMs and FBSMs.

This article proposes an enhanced common-mode voltage (CMV) injection method for fault-tolerant operation of cascaded H-Bridge (CHB) inverters, with the goal of achieving zero fundamental component in the injected CMV in the case of single-switch faults. By eliminating the fundamental component of CMV (FCMV), the suggested method prevents real power return from load to the dc-link of H-bridge cells at low-power factors, which is a critical issue in nonregenerative CHB inverters. The power flow back causes overvoltage in the dc-link capacitors of H-bridge cells in post-fault conditions and ultimately, the converter tripping off. Furthermore, the CMV increases voltage stresses and bearing currents in ac motor loads, and the proposed method reduces the peak-to-peak magnitude of the CMV while providing the maximum possible output voltage. The mentioned features enable safe fault-tolerant operation of the CHB converter across all load power factors, which is not possible with the existing fault-tolerant methods. Simulation results in MATLAB/SIMULINK and experimental validation on a laboratory prototype confirm that the suggested method effectively makes FCMV zero in the case of single-switch faults, offering improved safety and performance in fault-tolerant scenarios.

The rapid expansion of voltage source converter-based high voltage DC grids has made DC fault protection a critical research priority, due to low network impedance and the absence of natural current zero crossings. DC fault current limiters have emerged as an effective means of suppressing the rapid rise of fault currents and supporting coordinated protection strategies. This paper presents a comprehensive review of non-superconducting DC fault current limiter technologies for high voltage DC applications. A unified taxonomy categorizes existing concepts based on how inductors are realized, inserted, and dynamically reconfigured during fault conditions, while the review traces their historical evolution to highlight key development trends. Representative topologies are analyzed with respect to operating principles, dynamic performance, steady-state losses, and trade-offs among peak current suppression, breaker energy stress, and implementation complexity. Beyond classification, the paper identifies three key design dimensions: inductance selection, magnetic energy management, and coordination with converters and circuit breakers. The review concludes that effective deployment requires coordinated design across these dimensions to balance fault-current suppression, steady-state efficiency, breaker stress reduction, and practical implementation constraints. The paper also presents simulation case studies demonstrating the behavior of representative limiter topologies under common test conditions.

In this article, the hybrid modulated model predictive control ((HMPC)-P-2) method for the hybrid modular multilevel converter (hybrid-MMC) in high voltage direct current (HVDC) applications is introduced to improve the fault ride-through (FRT) capabilities on the direct current side (DCS). For the studied system, compared to conventional PI-based control method under DC short-circuit fault (DC-SCF) conditions, the proposed (HMPC)-P-2 demonstrates faster dynamics, lower dc and arm over-currents (reduced by 62% and 47%, respectively), moderate voltage fluctuations in submodule capacitors, and lower fault clearing (FC) time (reduced by 48%). While (HMPC)-P-2 shares the advantage of rapid dynamic response with model predictive control (MPC) techniques during fault conditions, it offers additional benefits over direct (DMPC) and indirect MPC (IMPC) methods, such as reduced computational complexity, independence from the converter's number of levels, and the elimination of the need for weighting factor tuning. As a result, the proposed method combines fast dynamic performance in DC-SCF conditions with ease of implementation on digital standard platforms. To validate the proposed method under DC-SCF conditions, simulations are conducted based on real high-power HVDC applications and MTDC grids in MATLAB/simulink. For comparing and experimental validation, the proposed (HMPC)-P-2, IMPC, and conventional PI-based methods have been implemented on a five-level (5L) hybrid-MMC setup based on ZYNQ module hardware in DC-SCF conditions, and the results confirm the claims.

This article proposes novel single-switch open-circuit (OC) fault detection and fault-tolerant methods for the recently introduced low-capacitance cascaded H-bridge static synchronous compensator (LC-STATCOM). Considering the superiorities of the LC-STATCOM, it is an appropriate solution for reactive power compensation. In the case of the submodule (SM) failures, however, maintaining the system's safe operation is a distinctive and more challenging subject compared to the conventional STATCOM due to the large twice fundamental frequency oscillations and fast dynamics of the capacitor voltages. By employing an online capacitor voltage waveform estimation and observation strategy, OC failures are quickly determined in less than one fundamental period without additional sensors. The faulty SM is bypassed entirely in the post-fault operation. Afterward, a fault-tolerant method based on the voltage reference modification technique is introduced to ensure continuous operation of the system under the faulty condition. The required converter over-design is minimized by defining an arbitrary clamp level concept rather than the fixed clamp in fault-tolerant methods. However, the voltage reference modification technique leads to unequal active power flow of the converter's phases. This results in capacitor voltages being unbalanced. The proposed method realizes capacitor voltage balance with a zero-sequence voltage injection-based control scheme. Eventually, the validity of the proposed strategy is verified by simulation and experimental test results.

This article addresses the challenge of fast and reliable dc fault protection in multiterminal direct current (MTdc) grids by coordinating a cost-effective hybrid-modular multilevel converter (H-MMC) with a hybrid dc circuit breaker (H-dcCB). The proposed method introduces a dc-fault-severity criterion that enables adaptive fault management at each station, thereby minimizing power fluctuations and shortening grid restoration time. The presented strategy employs an optimized full-bridge submodule (FB-SM) ratio in H-MMCs along with dc circuit breakers (dcCBs) that have low-peak-current-tolerance requirements, while maintaining selective dc fault protection. Simulations utilizing frequency-dependent overhead line (OHL) models in MATLAB/Simulink demonstrate that the fault current is limited to below 2.5 p.u. and cleared within approximately 4 ms. Experimental validation on a scaled-down three-terminal dc grid confirms the theoretical analysis and simulation results.

Open-circuit switch faults in submodules (SMs) of modular multilevel converters (MMCs) pose a significant challenge to system reliability and continuous operation. This article proposes a fault detection and localization (FDL) method that utilizes a neural network based on SeparableConv2D with a dataset generated from three-phase circulating currents and SM capacitor voltages. Considering the crucial role of controllers in MMCs and their influence on signal behavior during normal and fault conditions, a comprehensive control framework is employed in two operational modes: grid-connected and RL load-connected. This also ensures that the FDL method remains independent of the modulation scheme. This article considers faults even when the faulty switch is outside the arm’s current path. Preprocessing techniques, such as K-nearest neighbors (KNNs) imputation, quantile transformation, and sliding time window (STW), are used to prepare the data for optimal neural network input. Model optimization uses the AdamW algorithm, with learning rates dynamically adjusted via the ReduceLROnPlateau method. This approach minimizes computational complexity by requiring only one training session while leveraging optimized network architecture and preprocessing techniques to enhance FDL speed and accuracy. Finally, simulation and experimental results confirm the effectiveness of the proposed method.

In recent years, hybrid modular multilevel converters (H-MMCs), which employ both half-bridge submodules (HB-SMs) and full-bridge submodules (FB-SMs) in each arm, have gained significant attention in high-voltage dc (HVdc) systems. This article thoroughly investigates the behavior of an H-MMC with an arbitrary ratio of FB-SMs per arm, coordinated with a dc circuit breaker (CB), during a pole-to-pole short-circuit (SC) fault. Upon detecting an SC fault, the CB is activated, and the H-MMC is temporarily blocked to reduce the peak fault current. The behavior of the H-MMC during this short interval is highly nonlinear, and this article aims to provide a precise model to analyze the H-MMC's behavior and calculate arm currents, dc fault current, and voltage increase in the FB-SMs. The model accounts for all nonlinear states during the blocking state, including arm current decay and the effect of arm inductors on current commutation, which becomes critical when fast CBs or short dc lines are considered in HVdc systems. A new index is also introduced to compare the power switch requirements for various MMC and CB combinations as a function of the FB-SM ratio and CB interruption times. Finally, the analytical model and mathematical equations are validated through simulations and experimental testing on a scaled-down prototype.

This article presents an improved position sensor fault-tolerant control (IPS-FTC) of the stator current components of the permanent magnet synchronous generator (PMSG). It ensures the generator's operation in post-fault conditions, which are required for uninterruptible power injection by renewable energy conversion systems (RECSs). The proposed method is based on sliding mode (SM) theory and overcomes the drawbacks of traditional position sensor fault-tolerant control (PFTC) methods. The developed approach is relatively simple, direct, and robust versus non-modelled quantities. Furthermore, it does not require stator voltage sensors, compared to other developed SM control techniques. The stability and convergence of the proposed approach are proven by simulation and experimental results.

DC fault detection and identification are critical challenges in Multi terminal DC (MTDC) grids. Hence, developing a reliable method is essential to address this issue. This paper proposes a two-stage fault detection method based on discrete wavelet transform (DWT) and artificial neural networks (ANN) to enhance the reliability of MTDC grid protection. The proposed method is robust against MTDC grid transients (non-fault conditions) and variations in MTDC grid parameters. Moreover, a small dataset is used to train the network, reducing computational burden and faster fault detection. Besides, the sensitivity analysis has been performed to evaluate the proposed method in the Modular Multi-level Converter (MMC) parameter variations. Extensive simulations, including noise effects, are conducted in the MATLAB/Simulink environment to validate the proposed method.

The hybrid half-bridge (HB) and full-bridge (FB) modular multilevel converter (MMC) is recognized for its capability to handle de faults in high-voltage de (HVdc) systems. During a de fault, various fault management strategies are employed in the hybrid MMC to reduce the dc-side voltage and the fault current. These strategies have a significant impact on the performance of the MMC, particularly on the submodule (SM) capacitor voltages. This paper investigates different fault management strategies employed in hybrid MMC-based HVdc systems. The fault management strategies considered in this paper are based on the de fault current management achieved through active control and blocking SMs. In the active control mode, the de side voltage of the MMC is managed in a way to reduce the fault current after fault detection, while keep the control on the MMC. In another strategy, all the power switches are turned off temporarily, leading to the injection of counter-emf voltage by FB-SMs and current reduction. However, it will lose the control temporarily on the MMC current and voltages. In this paper, different aspects of these two techniques are compared, and the validity of the comparison is proved through simulation in Matlab/Simulink environment and experiments on a scaled down laboratory prototype.

Five-level nested neutral point clamped (5L-NNPC) converter is a compelling topology to use in renewable energy conversion, grid-connected facilities, and motor drives. However, an open-circuit fault (OCF) in any of the switches in the NNPC results in the inverter shutdown. Therefore, to tackle this issue, this article presents a comprehensive fault-tolerant strategy including OCF detection, diagnosis, and postfault operation in 5L-NNPC. As an IGBT switch fails, the failed switch is diagnosed through a model-based two-layer strategy. Furthermore, taking advantage of model predictive control (MPC) and reconfiguring the switching states, a postfault operation strategy with the ability to provide partial power is developed. Due to the OCF, some switching states are removed and the phase voltages are unbalanced in postfault conditions. Therefore, the weighting factors of the multiobjective cost function are tuned automatically to improve the functionality of MPC, especially, in terms of balancing the voltages of flying capacitors (FCs). Accordingly, the introduced method exploits the remaining capacity of the converter, while the voltages of the capacitors are maintained. Simulation and experimental results verify the accuracy of the detection and diagnosis method and also, the capability of the converter to supply partial power to the load after an OCF occurrence.

This article introduces a new fault-tolerant method for cascaded H-bridge (CHB) multilevel converters based on the selective harmonic mitigation (SHM) technique. In the proposed method, balanced line-to-line voltages are achieved by injecting a common-mode voltage (CMV) into the unbalanced phase voltages when the number of healthy cells differs among phases. The injected CMV allows maximum phase utilization using a minimum number of healthy cells. The suggested method imposes new constraints on SHM switching angles to avoid over-modulation. It also maximizes line-to-line voltage by injecting an appropriate CMV to the modulation waveforms. However, the fundamental component of CMV (FCMV) can cause uneven power distribution among CHB phases, leading to power flow-back in the inverter, which is problematic for nonregenerative CHB inverters as it increases the dc-link voltage of the cells. To avoid power flow-back during faulty conditions, minimizing FCMV is included as an additional objective in the SHM modulation technique. Simulation and experimental results confirm the effectiveness of the proposed fault-tolerant method.

Hybrid half-bridge (HB) and full-bridge (FB) modular multilevel converter (MMC) is recognized for its capability to handle dc faults in high-voltage dc systems. However, two critical challenges in the hybrid MMC (H-MMC) require further investigation: internal switch failures and dc faults. This article proposes an arm average value model (AVM) for the H-MMC to analyze dc faults and internal switch failure conditions. In the proposed AVM, each arm comprises FB submodules (FB-SMs), HB submodules (HB-SMs), and internal-fault SM (IF-SM), the latter representing the SM with internal switch failure conditions. Unlike conventional AVMs, it accurately captures H-MMC dynamics under such failures as well as during transitions between blocking and deblocking modes. Modeling the internal switch failure is useful in capturing the dynamic behavior of IF-SM required for fault-detection methods and fault-tolerant control strategies. Furthermore, by accurate estimation of H-MMC behavior during the recovery process after blocking, this model is highly useful for the design and tuning of control strategies, especially under dc fault recovery. Conventional sorting and balancing algorithms are incompatible with this model because they do not account for failed SMs; therefore, a dedicated algorithm is developed to evaluate their impact on H-MMC performance. The validity of the proposed AVM is demonstrated through simulations in the MATLAB/Simulink environment and experimental validation using a scaled-down laboratory prototype.

Protection against dc short circuits is a crucial challenge in multiterminal direct current (MTDC) grids due to the low-impedance characteristic of the dc grids. One of the promising solutions is using the multiline hybrid dc circuit breakers (MLH-DCCB), which recently acquired more attention owing to decreased power electronic devices, coordination capability, and selective fault isolation. This article presents a protection strategy employing a Thyristor-based MLH DCCB in coordination with the half-bridge modular multilevel converter (HB-MMC). The main merits of the proposed method are 1) limiting the fault current using the coordination technique between MMC and the proposed MLH DCCB; 2) employing a smaller size of current-limiting reactors and lower DCCB short circuit interruption requirement; 3) presenting the cost-effective and reliable protection system; and 4) providing the fast fault-clearing period and grid restoration procedure. The performance of the proposed coordinated dc fault protection strategy is validated in a four-terminal HVDC grid by the Typhoon HIL-404 real-time digital simulator. Also, the scaled-down dc grid prototype is implemented in the laboratory, and the experimental results are presented to confirm the theoretical analysis. A comprehensive comparison with the other protection approaches proves its superiority and effectiveness in terms of economy and fault-clearing performance.

This paper presents the optimization of the EMI filters for a multi-level flying capacitor boost converter (FCBC) by using a frequency-domain EMC model. The objective is to find optimal EMI filters design by estimating the EMI noise on the input and output sides simultaneously. A generic modeling process, suitable for any number of levels, is applied to a three-level flying capacitor boost converter for illustration. The model is developed and validated on an experimental prototype. Then, the filters are designed by an optimization process and validated by measurement. Finally, a sensitivity analysis on the impact of the number of levels and the switching frequency is performed.