For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully functional 256Mb SRAM test-chip with the smallest high density SRAM cell of 0.027um 2 is demonstrated down to 0.5V. The 4 th generation FinFET transistors are optimized with device mismatch reduction by 25%∼35% and multi-Vt device options to enable low power and high performance design requirements.

Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin capability of 450mV is achieved with variability reduction for the first time. Metal capacitance reduction by ~9% is realized with advanced interconnect scheme to enable dynamic power saving.

Being the dedicated IC foundry, TSMC provides a complete portfolio of technologies covering leading-edge technology, specialty technology, and 3D IC system integration technology to fulfill customer product needs in various market segments. While the leading-edge CMOS technology continues to extend Moore's law as a driver for business growth, More-than-Moore specialty technology leverages the logic technology platform with value-added components to enable various functionalities for a wide range of applications. In this paper, the evolution of advanced CMOS technology is reviewed. Challenges in scaling transistor, SRAM and interconnect are discussed. Examples of specialty technology will also be illustrated.

For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technology provides 2X logic density and >35% speed gain or >55% power reduction over our 28nm HK/MG planar technology. To our knowledge, this is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node. Low leakage (SVt) FinFET transistors achieve excellent short channel control with DIBL of <;30 mV/V and superior Idsat of 520/525 uA/um at 0.75V and Ioff of 30 pA/um for NMOS and PMOS, respectively.

An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described.

A 32 nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 muA/mum (n/p) are achieved at I off =100 nA/mum, V dd =1 V, 30 nm physical gate length and 130 nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 muA/mum (n/p) at total I off ~1 nA/mum @ V dd = 1V. Low sub-threshold leakage was achieved while successfully containing I boff and I goff well below 1 nA/um. Ultra high density 0.15 um 2 SRAM cell is fabricated by high NA 193 nm immersion lithography. Functional 2 Mb SRAM test-chip in 32 nm design rule has been demonstrated with a controllable manufacturing window.

For the first time, we present a state-of-the-art 32 nm low power foundry technology integrated with 0.15um2 6-T high density SRAM, low standby transistors, analog/RF functions and Cu/low-k interconnect for mobile SoC applications. To our knowledge, this is the smallest fully functional 2Mb SRAM test-chip for 32nm node. Low power transistors with Lg of 30nm achieve current drive of 700/380 uA/um at 1.1V and off-leakage current of 1 nA/um for NMOS and PMOS, respectively. An NPoly/NWell MOS varactor shows capacitance ratio of >5.0. The MOM unit capacitance of 3.5 fF/um2 is achieved with only 4 metal layers.

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.

Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring oscillators using HOT CMOS have been demonstrated for the first time, with L-poly about 85nm and t(ox) = 2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.