Identifying an Interconnect that will replace Cu will require the identification of a material that can meet a variety of materials design requirements and constraints. We propose an approach to simplify these hard to compute design to constraints into simple metrics. With the help of multi-objective optimization techniques, we are able to screen 15,000+ candidate metals rapidly. We present the workflow to identify candidate materials for high stack and low stack interconnects based on this approach.
In this paper, a new cascode, namely dual-gate (DG) MOSFET is designed and fabricated in 40nm CMOS technology to realize smaller area, reduced parasitic RC, and most importantly enhanced power gain up to 140GHz and ultra-wide bandwidth compared to the conventional cascode, aimed at D-band (110~170 GHz) amplifiers design.
For the first time, we apply fast measurement techniques to evaluate the positive bias stability of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with HfO 2 as the gate dielectric. Nonnegligible fast recovery characteristic of the abnormal threshold voltage (V th ) shift was recognized, and the significant difference between slow and fast measurements could be observed.
A novel bit-by-bit repair design innovation effectively repairs 1 bad bit by 1 redundancy bit and enables STT-MRAM technology to meet NV-RAM specifications and high yield. The test chip demonstrates 10ns Read/Write speed, 1E14 endurance and 125℃/10years retention.
We demonstrate ferroelectric switching in CeO2 doped Hf0.5Zr0.5O2 (HZCO) thin films and their applications for back-end-of-line (BEOL) compatible embedded memories. At low cerium oxide doping concentrations (2.0 - 5.6 mol%), the polar orthorhombic phase is stabilized after annealing at temperatures below 400°C. HZCO ferroelectrics show reliable switching characteristics beyond 1011 cycles in TiN/HZCO/TiN (MFM) capacitors, several orders magnitude higher than the identically processed Hf0.5Zr0.5O2 (HZO) capacitors, without sacrificing polarization and retention. We also report enhanced endurance (> 1010 cycles) in HZCO metal-ferroelectric-insulator-semiconductor (MFIS) stacks, which is promising for ferroelectric FET memory applications.
An experimental study of MIM decoupling capacitors placed in the BEOL of 300mm wafers using Al2O3 within HfO2 dielectric thin films is reported. By increasing aluminum concentration (7.9%-14.3%) within the dielectric insulator, a capacitance density of up to 27.6 fF/µm2 with linearity of 1610 ppm/(MV/cm)2 at 10kHz was achieved. J-E and dielectric breakdown characteristics at temperatures from -50°C to +150°C were analyzed. Low leakage current (<0.1µA/cm2) was measured for up to 100°C. Further, time-dependent dielectric breakdown reliability measurements under constant field stress were investigated over temperature (25-150°C). Capacitors reached 1000 years of extrapolated lifetime for all Al concentrations (7.9%-14.3%) at 25°C.
The electron scattering rate and mobility are investigated based on density-functional formalism. The results yield the low field mobility of about 180 cm2/Vs and 100 cm2/Vs for monolayer MoTe2 and WTe2 at room temperature, respectively. Due to the smaller effective mass, WTe2 exhibits the mobility significantly higher than that of MoTe2, suggesting its potential for transistor applications.
A method has been developed for depositing polycrystalline gallium nitride (GaN) thin films at low temperature (400 °C) with potential applications in the RF and microLED industries. [1] There is a need to deposit GaN directly on common substrates such as silicon, SiO 2 , and SiN to reduce the cost associated with using SiC wafers, especially for chiplet stacking or 2.5D integration. While ALD of GaN has been reported in the literature, the most common deposition techniques are MOCVD and MBE at high temperatures >700 °C. [1] , [2] The difference in high deposition temperature and low operating temperature often results in strained material with significant defect densities. [1] Herein we demonstrate the deposition of polycrystalline gallium nitride at a reduced temperature, 400 °C, using tris(dimethylamido)gallium (TDMAGa) and anhydrous hydrazine in an atomic layer annealing (ALA) process. It is possible that by depositing a GaN templating layer by ALA at low temperature may reduce inherent strain in the material and buffer layer thickness required to form device-quality GaN using further deposition by other techniques.
A double HfZrO 2 (HZO) ferroelectric field-effect transistor (FeFET) is demonstrated with ultra-low operating voltage as |V P/E | = 3 V to achieve multilevel cell (MLC) nonvolatile memory (NVM). Compared to a single FE-HZO FeFET, the metal/ferroelectric/metal/ferroelectric/Si (MFMFS) structure results not only in a reduction of V P/E , but also provides a feasible memory window (MW) of 1.9 V for MLC operation. In addition, the metal/ferroelectric/insulator/ ferroelectric/Si (MFIFS) FeFET exhibits a MW as high as >2.5 V. The double HZO FeFET has potential to improve power consumption and enhance memory density for MLC-NVM applications.
We demonstrate a wide temperature range and high thermal sensitivity radiometry image sensor by using a 32x32 pixels SPAD imager sensor with a time gated active reset circuit. The temperature range with upper limit of 1050 °C and lower limit of 280 °C can be detected with low noise, thanks to the high sensitivity performed by short deadtime and adjustable summed output of multi-pixel readout technology. The thermal image is detected with high spatial resolution of about 100 µm.
MoS2 is a typical two-dimensional (2D) semiconductor with extraordinary electrical properties, and has been intensively investigated as a channel material for field-effect transistors (FETs) and logic circuits in recent years. In this work, the top gated (TG) MoS2 FETs are fabricated with wafer-scale uniformity, and several pivotal devices and circuits based on MoS2 films are demonstrated, including current mirrors, inverter, and the AND/OR logic circuits. All devices exhibit reliable electrical characteristics, which lays the foundation for the future fabrication of large-scale MoS2 circuits.
We report ferroelectric (FE) laminate HSO/HZO MFMIS FeFETs. An MFM/MIS area ratio control enables low voltage operation and 105 endurance. FE lamination (2 × 10 nm, 4 × 5 nm) and low FE anneal reduce the FeFET variability. Impact of the stack (MFMIS), material type/lamination, and FE anneal are studied for enhanced FeFET reliability and reduced variability.
Single diffusion break (SDB) devices in FinFET technology are desirable and attractive for their minimum footage in aggressively scaled circuits. This paper reports fin-shape optimization efficiently improved SDB PFET device performance by up to 9%. More importantly, it was found that the performance benefit was case-dependent on fin shape. The performance improvement was observed on a straighter fin profile if fin bottom width was lower than a threshold point, while when fin bottom width was larger than the threshold point, fin top/bottom width ratio existed an optimal ratio at 0.54. This was verified and predicted through silicon-validated technology computer-aided design (TCAD) simulation.
The 6 stacked Ge 0.95 Si 0.05 nanowires without parasitic channels are realized by NH 4 OH + H 2 O 2 wet etching. High I ON per stack and per footprint are achieved thanks to the nanowire conduction and the electrons populated in the high mobility L 4 valleys. The reduced SS of 80 mV/dec and improved I ON /I OFF of 1.5E5 are obtained by the removal of parasitic channels compared to the 7 stacked Ge 0.95 Si 0.05 nanowires with the parasitic channels in our previous work. The high I ON of 120 μA per stack (4600 μA/μm per channel footprint) at V OV = V DS = 0.5 V is reached among the Ge/GeSi 3D nFETs.
A nanosized-metal-grain pattern-dependent model was proposed for work-function-fluctuation (WKF)-induced variability on the gate-all-around (GAA) silicon nanofin and nanosheet MOSFET (NF-FET and NS-FET). This model was developed by the perturbation of location metal grains with error correction (EC) and was validated by the 3D device simulation (3D-DS) with 5000 samples in low errors (error rate (ER) < 1%). The model can estimate the uncertainty of WKF-induced variability in huge patterns without executing 3D-DS to save the computational resources.
We demonstrate complementary carbon nanotube (CNT) field-effect transistors (CNFETs) at the 90 nm node on 200 mm substrates within a commercial silicon foundry. This work advances beyond the state-of-the-art by (1) realizing complementary p- and n-type CNFETs and complementary (CMOS) CNFET logic based on a fully lift-off-free process (versus prior work that relied on non-conventional lift-off processing), (2) introducing an atomic layer deposited (ALD) protective interfacial metallic layer for improved metal-CNT source and drain contacts, and (3) show this process is VLSI-compatible and wafer-scale with improved yield, uniformity, and performance versus prior art. Importantly, these improvements enable CNFETs to be seamlessly integrated within existing silicon fabrication infrastructure, as it relies on only existing tooling currently used for silicon CMOS production, is low-temperature (≤415°C) and thus still back-end-of-line compatible, and is wafer-scale across industry-standard ≥200 mm substrates.
CMOS Imagers have adopted 3D integration using Back-Side Illumination (BSI) technology, with 2 CMOS layers assembled using Wafer-to-Wafer and advanced Hybrid Bonding technology. Targeting innovative AI and Machine Learning application, for offering AI processing at the edge within the image sensor itself, this paper presents some new 3D design and technology solutions in order to build a 3-layer Smart Imager. The hybrid bonding technology for assembly of multi wafers with a capability below 1 µm pitch is shown as well as Through Silicon Via (TSV) of 2 µm pitch compatible with hybrid bonding. To offer Design Technology Co-Optimization (DTCO) capabilities, a Place & Route methodology is proposed with the associated PDKIT to benefit of fine pitch interconnects.
An embedded Artificial Synaptic Device (eASD) featuring high-performance and high-density characteristics with n-MOSFET’s high-k layer as memristive switching pairs in pure 28nm CMOS process is firstly proposed. Taking the advantages of reliable output constructed by complementary memristance states, the novel artificial synaptic device fully compatible to CMOS process is promising to be implemented in the neuromorphic AI computing chip for the coming high-speed neural network system.
Stacking 4 n-type vertical gate-all-around transistors (VFETs) on 2 pFinFETs can scale down a 6T SRAM bitcell into the footprint of only 2 transistors. The minimum operation voltage (V min ) considering workfucntion (WF) variation can be reduced to 0.59V by tuning pFET fin height (H fin ) to 15nm and nFET gate length (L gn ) to 20nm without increasing bitcell area. Applying the negative bitline (NBL) level of -80mV can further increase the write speed by 10%.
