Content distribution has become the predominant form of traffic over the Internet; yet, this shift has happened “over the top” from the point of view of the operator: the content is placed and distributed in content distribution overlays which relegate the operator to the role of a dumb pipe. However, content distribution would benefit from the operator’s involvement: the knowledge of the network, its topology, what features it supports, the congestion level of links, etc, would all improve the end-user experience while consuming content. Information-Centric Networks (ICN)[1-6] have been proposed to help the operator route to content. The network architectures suggest using content name for routing, so as to direct a request for a specific piece of content to the copy which maximizes the utility of the operator. Requesting an item by name, rather than by address, frees the operator to decide which location to use. The operator can then make its decision based upon availability of the content at multiple locations and the network conditions between the user and these locations. We argue further that Information-Centric Networks offer further benefits to the operator beyond selecting which cache to use. Namely, the use of a single globally unique name for content allows the operator to perform fined-grained resource allocation decision based on the properties of the content associated with this name. In this letter, we describe an architecture initially presented in [7,8] to construct an Information-Centric Network architecture with a centralized content management plane. This architecture extracts content meta-data from the content going through the network and uses this meta-data for resource allocation. We argue that content is the proper granularity for resource allocation, as it makes the resource allocation problem more deterministic rather than probabilistic. We will see how this framework can be expanded for mobile networks.

IVAN HUANG ROC GUO HARRY XIE ZHENGXIANG WU Huawei Technologies In the past few years, the boundaries between information technology (IT)—which refers to hardware and software used to store, retrieve, and process data—and communications technology (CT)—which includes electronic systems used for communication between individuals or groups—have become increasingly indistinguishable. The rapid convergence of IT and CT is taking place at three layers of technology innovation—cloud, pipe, and device—which are described in detail in this chapter. As a result of this convergence, industries are adapting and new industries are emerging to deliver enriched user experiences for consumers, enterprises, and the private sector. Several factors are driving the convergence of IT and CT and, consequently, contributing to the integration and transformation of cloud, pipe, and device technologies (Figure 1). For example, as the mobile penetration rate nears 90 percent globally, more people are able to communicate with each other through mobile devices. Many of these devices can interconnect through cloud computing services when accessed via the Internet. Adding to this momentum are innovations in smartphones, which allow users to send and download music and images, to use the Internet to purchase products, and to pay retailers and financial institutions electronically. In addition, more than 50 countries have invested in national broadband projects that lay solid foundations for bandwidths adequate to drive ICT convergence. After years of evolution, Internet services, telecommunications value-added services, and even media services are converging for both consumers and industry. Services carried by optical networks and other modern wireless “pipes” are moving to the cloud, and both industries and consumers are utilizing those services through a variety of integrated smart devices.

Unfairness is one of the major problems in WMN as each node operates not only as a host but also as a router, forwarding packets on behalf of other nodes that may not be within the direct wireless transmission range of their destinations and thereby adding delay and affecting the throughputs of the node. Addressing end-to-end unfairness in wireless mesh network is necessary for the network to be scalable otherwise; the expected network scalability will not be met. The unfairness investigation shows that the end-to-end unfairness in a wireless mesh network will affect the network scalability. Modification to the network layer has been proposed to include an additional queue, a weighted fair scheduler and a classifier to separate locally generated flow from the relayed flows at each node. This will make the traffic flows from all the sources in the network to achieve equal throughput at the destination irrespective of the number of hops traversed. Another unfairness issues is also investigated at the MAC layer as a result of adopting existing single hop MAC protocol to be used in this multi-hop mesh network.

The ultimate goal for a high speed serial link is t o lower the system Bit Error Rate (BER). While hardware results have the final say, simulati on plays a key role in checking the system feasibility and predicting the performance m argin. Systems applications often use SerDes components from multiple suppliers, requirin g IBIS-AMI models for simulation interoperability. AMI simulation can be used to ide ntify the marginal serial links in the overall system, among which are those that do not m eet BER requirements. The BER of these links can be improved by the utilization of f orward error correction (FEC) algorithms. This paper will present an end-to-end m ethodology in which AMI modeling techniques and existing serial link analysis is aug mented with FEC to improve BER performance. Author(s) Biography Xiaoqing Dong joined Huawei Technologies in 2006 as a signal int egri y research engineer, where she works on high speed active SI s imulation and measurement technology. She received her bachelor and master de grees in communications and information system from Harbin Institute of Technol ogy, for research in Information and Communication Engineering. Geoffrey Zhang has been with Huawei Technologies since 2009. He i s currently the CTO for the Interconnect Division. Prior to joining Huawei he worked for Texas Instruments, Lucent Technologies, Agere Systems, an d LSI Corporation. He has worked on various products including data converters, timi ng devices, read channel chips, and SerDes cores. He received his Bachelor and Master d egrees both in the Department of Electrical Engineering from Zhejiang University, Ch ina, and Ph.D. in microwave engineering from Iowa State University. Dr. Kumar Keshavan is Software Architect at Sigrity. Dr. Keshavan's e xp rtise includes circuit simulation, circuit extraction, channel sim ulation, and timing analysis. Dr. Keshavan has 25 years in the EDA industry. In the p ast he has worked as software architect at Cadence Design Systems. He was one of th founders of Velio, Inc. which was a pioneer in providing SerDes switching devices to the communication industry. Dr. Keshavan has also been an active participant in the EIA IBIS standards organization. More recently he was one of the initiators of the I BIS AMI standards for serial links. Ken Willis is a Product Marketing Manager at Sigrity, respons ible for advanced signal integrity solutions. He has more than 20 years of e xperience in the modeling, analysis, design, and fabrication of high-speed digital circu its. Prior to Sigrity, Ken held engineering, marketing, and management positions wi th Tyco, Compaq Computers, Sirocco Systems, Sycamore Networks, and Cadence Des ign Systems. Zhangmin Zhong joined Sigrity as a Senior Application Engineer in 2009. Prior to joining Sigrity he worked for IO Methodology Inc., Cadence Design Systems, AlcatelSbell and Huawei Technologies. He has worked on var ious products and focused on high speed circuit designs. He received his Bachelor and Master degrees both in the Department of Electrical Engineering from Sichuan U niversity, China. Adge Hawes is a Development Architect for IBM at its Hursley Labs, United Kingdom. He has worked for IBM for more than 30 years across such hardware as Graphic Displays, Printing Subsystems, PC development, Data Compression, and High-Speed Serial Links. He has represented the company in man y standards bodies such as PCI, SSA and Fibre Channel. Currently he develops simula tors for IBM's High Speed Serial Links. Introduction With the release of the IBIS 5.0 specification, Alg orithmic Modeling Interface (AMI) syntax has provided an industry standard means with which to model the complex adaptive equalization functionality seen in modern SerDes (serializer/deserializer) devices. For example, transmitter Feed Forward Equa lization (FFE, or pre-emphasis) and receiver Decision Feedback Equalization (DFE) can b e efficiently modeled with AMI techniques. This has provided simulation interopera bility for engineers working with SerDes from multiple suppliers. Few serial links are designed completely from scrat ch; most have restrictions due to cost or compatibility (ex. existing PCBs, backplanes, co nnectors) that often limit significant BER improvements. Limited by legacy hardware, elect rical engineers are still able to improve system performance by certain “soft” method s implemented in ASIC front-end logic or on-board Field Programmable Gate Arrays (F PGA), such as line coding and error correction. Used extensively for optical links, err or correction methods are now beginning to find application in multi-gigabit elec tri al serial interfaces. A prototype flow for the incorporation of error cor rection into serial link analysis is proposed and exercised in a case study. The propose d fl w is as follows: 1. For the channels of interest, S-parameter models ar acquired from measurement using a high bandwidth Vector Network Analyzer (VNA ) 2. To produce raw bathtub curves (without error propag ation), serial link signal integrity analysis is performed using commercial ED A (electronic design automation) software and IBIS-AMI models 3. Marginal or failing serial links are identified as candidates for FEC 4. Performing error propagation calculation; during th is process the converged DFE tap coefficients from simulation are used to comput e the burst error voltage offsets, which in turn serves as the basis for FEC performance analysis, producing the burst error order of the serial link 5. Error correction analysis, to predict the BER perfo rmance enhancement In multi-gigabit serial links, DFE is often used at the SerDes receiver for reducing channel inter-symbol interference (ISI) and enhanci ng link performance. However, DFE can also introduce problems such as error propagati on, which can lead to burst errors. The DFE operation can provide some key insight into the burst errors that contribute significantly to BER degradation. A “slicer” algori thm can be utilized together with the DFE coefficients to calculate error propagation, an d predict the burst error order of the serial link. With the cumulative BER performance computed, inclu ding burst errors, forward error correction (FEC) algorithms can be applied to exami ne potential improvements in BER. These FEC algorithms can include: • FEC that deals with random errors (BCH code) • FEC that deals with single burst errors (Fire code) • FEC that deals with multiple burst errors (RS code) Both simulation and experiments to date have shown that particularly bad channels will fail their associated BER requirements even with FE C on. However, other marginal channels have shown an improvement in BER margin by as much as 10^3. These initial trials indicate FEC may not be a panacea, but may b e an effective way to enhance the BER margin for marginal channels in existing hardwa re. This paper will cover the entire end-to-end serial link simulation process, which includes: • Current “standard” serial link simulation process • IBIS-AMI modeling, and the utilization of these mod els in simulation • Bathtub curve generation for initial BER prediction by EDA tools • Eye quality metric – weighted eye • Error correction theory and methods • Prediction of BER improvement expected by utilizing error correction techniques Serial Link Simulation Process The current state-of-the-art for multi-gigabit seri al l nk signal integrity (SI) simulation involves convolution of the channel’s impulse respo nse with a large bit stream stimulus to produce time domain waveforms. The “channel” in th s context refers to the analog circuit comprised of the output stage of the SerDes transmitter (Tx), the input stage of the SerDes receiver (Rx), and the passive interconnect between the two. This interconnect can consist of circuits for the printed circuit boa rd (PCB), packages, connectors, etc. as shown in the Figure below. Figure 1 – Serial link simulation flow The impulse response can be generated by either fre quency or time domain techniques. The channel can be represented with S-parameters, a nd inverse FFT (Fast Fourier Transform) techniques can be used to produce the im pulse response. Also, traditional time domain Spice circuit simulation can be used to produce a step response, from which the impulse response can be directly computed. Usin g advanced convolution techniques, simulation can be both very fast and very accurate, enabling the simulation of a million bits or more in a minute or two. IBIS-AMI Modeling With the release of the IBIS 5.0 standard, algorith m c modeling for SerDes equalization became a standard practice, allowing the adaptive e qualization behavior of SerDes devices to be efficiently included in SI simulation s. There are essentially two APIs (application programming interface) defined in the IBIS standard as part of the Algorithmic Model Interface (AMI): • AMI_Init > allows impulse response modification • AMI_GetWave > allows waveform modification These are shown in the figure below. Figure 2 – IBIS-AMI APIs The AMI_Init function is used for equalizers (EQ) t ha perform one-time adaptation, meaning that they adapt their EQ settings once for the specific channel. This is common practice for SerDes transmitters that use Feed Forw ard Equalization (FFE, pre-emphasis, de-emphasis). The AMI_GetWave function is used for real-time adaptive EQs, and finds common application in receiver Decision Feedback Eq ualization (DFE), where the EQ is constantly adapting based on the waveforms it recei v s. So how would this fit in with the serial link simul ation methods described in the previous section? Let’s take for example a case where the Tx uses an algorithmic model with FFE and the Rx uses one with DFE. The sequence of event s for simulation would be as follows: • Impulse response generation (with EQs off) • Impulse response is modified by the Tx algorithmic odel (AMI_Init function) • Modified impulse response is convolved with the