This paper compares three different BER extrapolation methodologies for the ADC-based SerDes architecture design. It shows that Dual-Dirac method is the most accurate for BER estimation. This is further demonstrated through practical examples from IBIS-AMI model simulations of an ADC-based PAM4 SerDes design.

Jitter is amplified in any lossy system due to the channel loss. The amplification occurs at any jitter frequency below Nyquist. Jitter amplification grows exponentially with jitter frequency and data rate. Due to the complexity and lossy system behavior in NAND Flash memory system, duty cycle distortion (DCD) jitter exhibits a unique trend of jitter amplification. Jitter degrades the performance of NAND Flash memory system by limiting the maximum achievable data rates. It is extremely important to accurately apply the jitter in input stimulus while analyzing the system performance to capture the amplification effect. This paper focuses on the importance of DCD jitter analysis in higher-speed and heavier-loading NAND systems, and introduces a statistical approach to DCD jitter analysis.

The design solution space for high-speed serial links is becoming increasingly complex as data rates climb, channel topologies become more diverse, and tuning parameters for active components multiply. PCI-Express Gen-4 is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle. This paper is intended to help system engineers navigate through these design challenges by providing a how-to guide for defining, executing, and analyzing system-level simulations including PCIe Gen-4 Root Complex, Repeater, and End Point. Authors Biography Yongyao Li is currently the principal engineer at Huawei Technologies where he is responsible for high-speed system design of leading server and storage products. He received his MSEE from University of Electronic Science and Technology of China, and has over 14 years of experience in the area of signal and power integrity. Casey Morrison is a Systems Engineering Manager in the Data Path Solutions product line at Texas Instruments. His primary role at TI for the past eight years has been architectural definition, system simulation, and validation of high-speed interface products. His industry experience is in the area of high-speed serial communications and signal integrity spanning numerous interface standards including Ethernet, PCI-Express, SAS/SATA, and others. He received his Masters of Science in Electrical Engineering from the University of Florida. Fangyi Rao is a master R&D engineer at Keysight Technologies. He received his Ph.D. degree in theoretical physics from Northwestern University. He joined Agilent/Keysight EEsoft in 2006 and works on Analog/RF and SI simulation technologies in ADS. From 2003 to 2006 he was with Cadence Design Systems, where he developed SpectreRF Harmonic Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and medical imaging. Cindy Cui is an Application Engineer with the EEsof Team at Keysight. She received her Master’s degree in Micro-Electronics from Tianjin University. She has over six years of service and support experience on high-speed digital, RFIC design, and device modeling at Keysight. Her focus is mainly on DDR4 Design, PCIe, IBIS modeling and the correlation between simulation and measurement. Before Keysight, Cindy worked at Cadence for four years as the Application Engineer for Cadence simulation platform. Geoff Zhang received his Ph.D. in 1997 in microwave engineering and signal processing from Iowa State University, Ames, Iowa. He joined Xilinx Inc. in June, 2013. Geoff is currently Distinguished Engineer and Supervisor, in transceiver architecture and modeling under SerDes Technology Group. Prior to joining Xilinx he has employment experiences with HiSilicon, Huawei Technologies, LSI, Agere Systems, Lucent Technologies, and Texas Instruments. His current interest is in transceiver architecture modeling and system level end-to-end simulation, both electrical and optical. Introduction The design solution space for high-speed serial links is becoming increasingly complex as data rates increase, channel topologies become more diverse, and tuning parameters for active components multiply. PCI-Express (PCIe) Gen-4 is a particularly relevant example of an application whose design solution space can be a daunting problem to tackle, especially when each link can contain three active components: Root Complex (RC), Repeater, and End Point (EP). This paper presents a how-to guide for defining, executing, and analyzing system-level simulations involving all three components. The use of a Repeater to extend the reach between RC and EP over extremely lossy channels is a common practice and can present unique challenges in examining the design solution space. The Repeater’s settings must be co-optimized together with SerDes transmitter (Tx) and receiver (Rx) settings to maximize the overall link performance. The sections which follow present a how-to guide for performing end-to-end system-level simulation analyses involving Tx, Repeater, and Rx with a focus on PCIe Gen-4 channel topologies. The approach is based on IBIS Algorithmic Modeling Interface (IBIS-AMI) simulations. IBIS-AMI’s standardized interface offers interoperability between models provided by different integrated circuit (IC) vendors. More importantly, critical component-level impairments such as non-linearity and device noise can be represented in IBIS-AMI models and reflected in the overall link performance—effects that standard sparameter representations of equalizer components fail to capture. For the purposes of this paper, a Xilinx FPGA SerDes is used for the RC and EP; and a Texas Instruments Linear Repeater is used in between the RC and EP to achieve reach extension. The methodology outlined here can be extended to any RC, Repeater, and EP device. The proposed methodology for simulating the solution space of a Tx+Repeater+Rx system in the context of PCIe Gen-4 is as follows: 1. Determine if a Repeater is required 2. Define a simulation space 3. Define evaluation criteria 4. Execute the simulation matrix and analyze the results The goal is to reach a conclusion regarding the optimum configuration of the system in an efficient and timely manner. Step 1: Determine if a Repeater is Required Before evaluating a Tx+Repeater+Rx link, you must first understand whether a Repeater is required for the link. There are a few ways of reaching this conclusion, and they vary in complexity. 1. Compare the end-to-end channel insertion loss (RC to EP) to the PCIe channel requirements. Section 9.4.1.2 of the PCIe Base Specification (Rev. 4.0, Version 0.7 as of this paper’s publication) calls for a maximum channel loss of 28 dB at 8 GHz, including the RC and EP package loss. If the system channel loss exceeds this, then a Repeater is required. 2. Alternatively, a channel’s s-parameter can be simulated in a tool such as the Statistical Eye Analysis Simulator (seasim) together with a reference transmitter, reference transmit-side package model, reference receive-side package model, and a reference receiver to determine the post-equalized eye height (EH) and eye width (EW). If the EH and EW fail to meet the requirements set forth in Section 9.5.1.6 of the PCIe Base Specification, then a Repeater is required. In this paper, the following two-connector PCIe channel topology is considered. Although every PCIe link has both a downstream (RC-to-EP) direction and an upstream direction (EP-to-RC), this paper focuses on analyzing the downstream direction. A similar analysis can be performed for the upstream direction.

The current DDR4 specification for the receiver (Rx) sensitivity defined at the Rx input does not account for equalization functionalities implemented in advanced Rx designs and may lead to over-design. In this paper we present a novel approach to characterize the Rx sensitivity impact on Rx post-equalization signal. We demonstrate that at the Rx output timing impairment is induced by common mode variation. The resulting jitter can be represented by a deterministic jitter model and incorporated in the statistical eye calculation. Timing margin and jitter in the post-equalization eye is measured at Vref to eliminate over-design. Author(s) Biography Yong Wang is currently a Sr. Director of Engineering at Xilinx leading Device Power and Signal Integrity Group since 2011. His team owns Xilinx product families’ SI/PI methodology development, noise/timing/jitter analysis, interface timing such as DDR4/3, and corresponding verification/characterization. Prior to joining Xilinx, Mr. Yong Wang has been system design lead and SI/PI lead of several companies such as NVIDIA, MetaRAM, HP/Intel. He led the world first 16GB and 32GB R-DIMM design, validation and production with patented memory buffer ASIC design when he was system lead with MetaRAM. In NVIDIA/HP/Intel, he provided technical leadership in the areas such as but not limited to, IA-64 system front-side parallel bus channel timing, serial link channel analysis, system level power modeling, on-die power grid noise/timing analysis and timing/noise validation in the lab. Mr. Yong Wang received his M.S. degree in Electrical Engineering from Colorado State University and B.S. degree in Electrical Engineering from Peking University. Mr. Yong Wang has 21 US patents issued and several publications including best paper rewards in conferences like EPEP and ECTC. Thomas To is a Technical Director in System Memory Signal Integrity & Device Power Group at Xilinx, Inc. Prior to joining Xilinx, Thomas was with NVIDIA Advanced Technology Group focused on high speed (32GTs) circuits & system channel designs and supported different test chips for different advanced process nodes such as 20nm SOC & 16nm FINFET process. Before NVIDIA, Thomas worked for Intel for more than 16 years covered and led many different types of system memory IO development such as Sandy Bridge Server DDR IO and covered many different system memory technology ranging from DDR1 to DDR4. Thomas received his PhD degree in Electrical Engineering from the Ohio State University in 1995 & he has over 37 patents in the fields of mixed signal IO circuits and system memory configurations as well as high speed clocking for high speed memory designs. Penglin Niu is an engineer manager at Xilinx. Her team is responsible for SI/PI modeling methodology, and product SSN and PDN analysis. She was the signal integrity lead for memory interface in Xilinx before the management position. Prior to Xilinx, she worked for Intel as signal integrity lead and package design lead. She was deeply involved in high speed DDR3/DDR3L system design and high performance CPU package design. Penglin received her Ph.D. degree from University of Illinois Urbana-Champaign, and M.S. degree from University of Missouri-Rolla. Fangyi Rao is a master engineer at Keysight Technologies. He received his Ph.D. degree in theoretical physics from Northwestern University. He joined Agilent EEsof in 2006 and works on Analog/RF and SI simulation technologies in ADS and RFDE. From 2003 to 2006 he was with Cadence Design Systems, where he developed the company's Harmonic Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and medical imaging. Juan Wang is a Staff Signal Integrity engineer at Xilinx Inc. She has been focusing on memory interface timing analysis such as DDR4/DDR3/RLDRAM3 and corresponding lab verification. Prior to Xilinx, she worked for Juniper as signal integrity engineer for more than 5 years supporting system design 10GE/XFI/XLAUI/SFI/sGMII/rGMII/PCIE/DDR3 signal integrity modeling, simulation and measurements. Juan received her MSEE from University of Missouri-Rolla and Tsinghua University. Xi (Sean) Long is a senior Signal Integrity engineer at Xilinx Inc. His work at Xilinx focus on timing analysis and lab validation of DDR memory interface. Prior to Xilinx, he was with Nvidia Corp as a Mixed Signal Design/Validation engineer working on circuit design and lab validation of analog blocks in DDR and SERDES interfaces such as LPDDR4/GDDR5/PCIE. He received his MSEE from University Delaware

Correlation between inter-symbol-interference (ISI), duty-cycle-distortion (DCD) and random jitter (RJ) at data channel output is investigated. Jitter components are extracted by comparing crossing time data between repeated simulations under different input jitter conditions. The results show that due to channel dispersion, DCD and RJ RMS at a given output edge depend on the pattern of neighboring bits and vary between edges, leading to correlations between output DCD, RJ and ISI.

Effects of transmit jitter on lossy clock channel are analyzed analytically by treating the 1010 input clock signal as a sinusoidal wave with a phase modulation that represents jitter. Jitter-to-amplitude-modulation transfer functions are derived for sinusoidal jitter and random jitter in terms of the signal transfer function or S-parameters. Input jitter is shown to induce amplitude modulation in the output signal as a result of channel dispersion, leading to voltage noise at the channel output. RJ induced voltage noise is found to scale uniquely with channel loss. To verify the theory, numerical simulations are performed on channels with different losses and at various data rates. The input clock signal is represented with a square wave, and the output signal is calculated by linear superposition of the channel step response. Theoretical and simulation results are found to be in excellent agreement.

IBIS Algorithmic Modeling Interface (IBIS-AMI) defines two approaches to SerDes modeling and simulation flow: time domain or bit-by-bit simulation for nonlinear and/or time variant (NLTV) model and statistical simulation for linear and time invariant (LTI) model. Statistical simulation has advantages of faster simulation speed and arbitrary low BER floor under linear model assumption. However, majority high speed SerDes devices incorporation clock and data recovery (CDR) circuit and/or adaptation state machines which are not conducive to LTI modeling. This paper presents a unified SerDes modeling method for both simulation types. The results show close correlation between time and statistical simulations based on selected criteria. This paper demonstrates the feasibility of dual model approach to IBIS-AMI and summarizes simulation methods that are unique to each.

Clock channel jitter amplification factor in terms of transfer function or S-parameters is derived. Amplification is shown to arise from smaller attenuation in jitter lower sideband than in the fundamental. Amplification scaling with loss is obtained analytically.

Statistical analysis provides an efficient alternative to the traditional Monte Carlo simulation for extremely low BER calculation in high speed serial link designs. Transmitter (TX) jitter posts a huge challenge in statistical simulation due to its pattern- and time-dependent nature and the resulting computational complexity. This paper presents a fast yet rigorous approach to calculate TX jitter in statistical simulation based on physical models of various jitter components. The approach accurately captures effects of uncorrelated random jitters, jitter amplification by channel dispersion, frequency dependency of periodic jitter and data duty-cycle-distortion.

This paper proposes an efficient method for 2-D EM-based simulation of multilayer transmission lines making use of causal, frequency-dependent dielectric loss models. Frequency-dependent loss modeling overcomes causality violations introduced by classical, static loss descriptions, but it poses significant challenges to efficient applications of EM-based models in both time and frequency-domain circuit simulations. The proposed method overcomes this challenge by introducing a modeling approximation which preserves causality, maintains accuracy and achieves speed-up of several orders of magnitude compared to direct application of the frequency-dependent dielectric loss model in EM-based simulations.

In the signal integrity industry, S-parameters have become the most commonly distributed models for simulating passive components. Because S-parameters are frequency-domain values, many signal integrity engineers are finding it difficult to accurately implement these parameters in time-domain simulations. Addressing transient convolution specifically, this paper shows the need for a new impulse response model and proposes a methodology for its inclusion in time-domain simulations. The paper also solves another difficult problem by presenting a new technique for converting band-limited S-parameters into 'base-delay' causal and passive impulse response models that preserve accuracy to the maximum frequency of the original S-parameters. Fangyi Rao received his Ph.D. degree in physics from Northwestern University in 1997, for research in quantum theory of magnetism and transport. He joined Agilent EEsof in 2006 as a Senior Development Engineer, where he works on Analog/RF simulation technology in ADS and RFDE. From 2003 to 2006 he was with Cadence Design Systems, where he made key contributions to the company's Flexible Balance technology and perturbation analysis of nonlinear circuits. Prior to 2003 he worked in the areas of EM simulation, nonlinear device modeling, and optimization. Design group of Tyco Electronics as a signal integrity engineer, specializing in the analysis & design of high-speed, high-density components. Currently, he is a Member of Technical Staff with Tyco Electronics, where he focuses on high-frequency measurement & characterization of components & materials, full-wave electromagnetic modeling of high-speed interconnects, and the simulation of digital systems. Mr. Morgan's responsibilities at Tyco Electronics include numerous research activities, and he has presented multiple papers at both DesignCon & IMS. Sanjeev Gupta, the Signal Integrity Applications Expert in the EEsof EDA Division of Agilent Technologies, has over eighteen years of experience in high frequency design and simulation. Before joining Hewlett Packard, he worked as a high frequency design engineer/scientist at the Defense Research and Development Organization in India. His background includes the design and development of 100 MHz to 100 GHz active and passive circuits for a wide variety of applications. His most recent activity is focused on influencing the Signal Integrity Design Flow in ADS. He received a Master's Degree in Microwave Engineering from the University of Delhi, India in 1988. Sanjeev was awarded the Hewlett Packard President's Award in 1998 for his contributions to the company. of Simulation Technology, where he made several key contributions to the company's harmonic balance technology, oscillator analysis, and phase noise simulation.