We investigate the electrical characteristics according to changing temperature on trap distribution in the energy gap of grain boundary (GB) and interface trap density (D(it)) between polycrystalline-silicon (poly-Si) channel and tunnel oxide in Vertical NAND (VNAND) flash cell with poly-Si channel. We confirmed that there are two factors changing GB potential barrier height such as trap distribution in GB and D(it) using technology computer-aided design (TCAD) simulation. Also, we found that the electrical characteristics according to changing temperature are significantly dependent on height and position of GB potential barrier in VNAND flash cell with poly-Si channel. We expect that it is required to develop more accurate extraction method for trap distribution in each GB and D(it) for better understanding temperature dependence of electrical characteristics in VNAND Flash cell.

We investigated the stress distribution and electrical characteristics according to changes in the process parameters in a vertical NAND (VNAND) flash cell with a poly-Si channel. We used technology computer-aided design to confirm that process parameters changes affect the stress distribution in a VNAND flash cell and the stress in the poly-Si channel. Also, we found that, as the stress distributions changed, the electrical characteristics depended significantly on the annealing temperature, channel hole angle, and tungsten intrinsic stress in a VNAND flash cell. Thus, the industry needs to develop and apply better process parameters and acquire a better understanding of how the electrical characteristics of a VNAND flash cell depend on those parameters.

We present a novel device architecture for low set and reset currents in phase change random access memory (PCRAM). In this structure, the sidewall of phase-change film is contacted with the vertical heating layer. In particular, to realize a small contact area of under 50 nm(2) for low reset current, this structure includes stacked layers consisting of extremely thin phase change material (PCM) and conduction films, the fabrication method of which is proposed. We estimated set and reset currents for the proposed structure by the device simulation method. Here, we confirmed that a contact area of 30 nm(2) in this structure, where Ge2Sb2Te5 is used as PCM, provides a reset current of 13.5 mu A and a set current of 4 mu A, which are promising for the scaling down of PCM. Furthermore, it is confirmed that the thinner PCM in this structure provides less thermal disturbance to the neighboring cell. From the results, we expect this structure to be a promising candidate for a high-density nonvolatile memory architecture with PCM. (C) 2015 The Japan Society of Applied Physics

The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage (V-T) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.

We present analytical on-state drain current model of 2-dimensional (2D) planar-type poly-Silicon TFT devices. The effect of grain and grain boundary on the carrier transport of 2D poly-Silicon devices has been studied by simulation (matlab) tool. Especially, we considered physical parameters such as grain length (Lg), grain boundary length (Lgb) and grain boundary trap density (NGB) in order to analyze cell performance of the poly-Silicon materials at various temperature. Thus, we simulated the temperature dependence of the on-state drain current within a wide temperature range from 248 K (-25 °C) to 348 K (75 °C). From these results, we confirmed that grain length and grain boundary trap density significantly effects on-state drain current in poly-Silicon materials.

We present an investigation of the retention characteristics of three-dimensional (3D) gate-all-around metal–oxide–nitride–oxide–semiconductor (GAA-MONOS) devices. The effect of retention charge loss in 3D GAA-MONOS devices at elevated temperatures has been experimented and studied by technology computer-aided design (TCAD) simulation. In particular, we considered the dependence of the trap energy level in the silicon nitride layer on the retention characteristics of the 3D GAA-MONOS devices by TCAD simulation. Here, simulation results showed that acceptor trap energy level considerably affects the retention charge loss compared with donor trap energy level in the silicon nitride layer that has a Gaussian trap distribution. Moreover, as the acceptor trap energy level becomes shallower, the effect on retention charge loss increases with increasing temperature. From these results, we confirmed that the simulation results for the retention characteristics of 3D GAA-MONOS devices were in reasonable agreement with the experimental results.

We present an investigation of the program and erase speed characteristics of three-dimensional (3D) gate-all-around (GAA) metal–oxide–SiNX–oxide–silicon (MONOS) cells. The effect of the tunneling oxide layer thickness in 3D GAA MONOS cells has been experimentally investigated and studied by 3D technology computer-aided design (TCAD) simulation. In particular, we considered physical parameters such as trap density, capture cross section, and trap level in order to analyze the physical properties of the silicon nitride layer. Simulation results indicated that the trap density significantly affects the program efficiency compared with other physical parameters, and the trap level mainly affects the erase efficiency. From these simulation results, we confirmed from the experimental results that the modeling accuracy is about 80%. Moreover, the simulation results for the program and erase speeds of the GAA MONOS cells were in reasonable agreement with experimental results.

A bit-cost scalable (BiCS) NAND flash memory with a bulk erasing method is investigated in view of cell characteristics and uniformity. The proposed cell array has an additional electrode layer for a bulk erase operation in the middle of a vertical channel string cell. Here, under a bias condition of 20 V, a programming threshold voltage of 4.2 V at 1 ms and an erasing threshold voltage of V th = -1.5 V at 10 ms are confirmed, which is acceptable for flash memories. Furthermore, the shielding transistor close to an erase electrode is also investigated, which gives better erase characteristics for the cells adjacent to the erase electrode. From this result, we expect that a bulk erasable-BiCS technology with a shielding transistor can be a candidate three-dimensional (3D) NAND flash memory.

The cell characteristics of an alloy FePt nano-dot (ND) charge trapping memory with a high-k dielectric as a blocking oxide was investigated. Adoption of a high-k Al2O3 material as a blocking oxide for the metal nano-dot memory provided a superior scaling of the operation voltage compared to silicon oxide under a similar gate leakage level. For the 40-nm-thick high-k (Al2O3) blocking oxide, we confirmed an operation voltage reduction of ∼7 V under the same memory window on for silicon dioxide. Also, this device showed a large memory window of 7.8 V and a low leakage current under 10−10 A in an area of Φ 0.25 mm. From these results, the use of a dielectric (Al2O3) as a blocking oxide for a metal nano-dot device is essential, and a metal nano-dot memory with a high-k dielectric will be one of the candidates for a high-density non-volatile memory device.

A bit-cost scalable (BiCS) technology using a bulk erasing method instead of the conventional erase operation using gate-induced drain leakage (GIDL) is proposed to realize better cell characteristics and process feasibility for three-dimensional (3D) NAND flash memory. This has an additional electrode layer for a bulk erase operation in the middle of a vertical string cell. Here, we confirmed that this structure using an additional electrode provides good program and erasing speed by simulation. Furthermore, junction engineering is performed to realize a polysilicon layer of the flat plate type as a bulk electrode for better design feasibility. From this result, we expect that a bulk erasable BiCS technology using a flat plate erase electrode can be a candidate 3D NAND flash memory technology.

A two-terminal N+/P/N+ Si junction device that can replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque magnetic random access memory (STT-MRAM), by three-dimensional device simulation. An N+/P/N+ junction structure with 30×30 nm2 area provides sufficient bidirectional current flow to write data by a drain-induced barrier lowering (DIBL) under a reverse bias at the N+/P (or P/N+) junction, and high current on/off ratio of 106, which is acceptable for STT-MRAM. In this work, critical parameters such as P-length, P doping, and N+ doping are investigated to elucidate the optimal parameter condition in view of write current and current on/off ratio.

We propose a bilateral switching poly-Si junction device to realize a crossbar array with a perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM). An N+/P/N+ bilateral junction device with two bias terminals provides bidirectional current flow enough to write STT MRAM by a drain induced barrier lowering under a reverse bias of N+/P. In addition, asymmetrical doping for two N+ terminals provides a high on-off ratio of 10(7) under read condition, which is acceptable for a crossbar array. From this work, it is expected that a bilateral poly-Si junction will be a promising switch device to achieve crossbar architecture with a perpendicular STT MRAM.