An atomistic understanding of dry-etching processes with reactive molecules is crucial for achieving geometric integrity in highly scaled semiconductor devices. Molecular dynamics (MD) simulations are instrumental, but the lack of reliable force fields hinders the widespread use of MD in etching simulations. In this work, we develop an accurate neural network potential (NNP) for simulating the etching process of amorphous Si3N4 with HF molecules. The surface reactions in diverse local environments are considered by incorporating several types of training sets: baseline structures, reaction-specific data, and general-purpose training sets. Furthermore, the NNP is refined through iterative comparisons with the density functional theory results. Using the trained NNP, we carry out etching simulations, which allow for detailed observation and analysis of key processes such as preferential sputtering, surface modification, etching yield, threshold energy, and the distribution of etching products. Additionally, we develop a simple continuum model, built from the MD simulation results, which effectively reproduces the surface composition obtained with MD simulations. By establishing a computational framework for atomistic etching simulation and scale bridging, this work will pave the way for more accurate and efficient design of etching processes in the semiconductor industry, enhancing device performance and manufacturing precision.

Reliabilities of high voltage transistors has become a major concern for NAND tech scaling. In this work, we investigate reliabilities of HVN transistors. When a high bias stress was applied, large degradation of HVN transistors has been observed. This degradation has been attributed to electron injection with high energy by FN stress. We have found that the Vt shift of HVN causes malfunction of the circuit operation, and we have suggested the fail criteria of HVN for precise evaluation.

In DRAM manufacturing, HK dielectric stacks with HfO2/HfSiOx are being used as a replacement for conventional silicon oxide dielectrics for high speed. One of the major problems is reliability of gate dielectric. Especially, non-Weibull distribution in PMOS TDDB has been observed. This abnormal behavior has been attributed to the effect of HKMG bi-layer structure and the Tinv variation. Finally, we suggest precise method for lifetime extraction in this abnormal case.

The formation of high-energy electrons and ion fluxes induced by an abnormal electron heating mode in asynchronous pulse-modulated plasma was investigated using particle-in-cell simulation. We demonstrate that the abnormally high electron heating mode was induced only for a short time in the asynchronous pulsed plasmas. Furthermore, enhanced production of energetic electrons accompanies this electron heating. In particular, the higher energy electrons (ε > 20 eV) are mainly produced by the abnormal electron heating during the first period of the abrupt sheath expansion phase in the asynchronous pulsed plasma with α1 = α3 = 0.05. These high-energy electrons are crucial for tailoring the expansion of plasma density and neutralizing the surface charging for the HARC etching process. A synergy of higher energy electrons and higher density ion fluxes in asynchronous pulsed plasma can be a promising solution to reduce statistical variation and charging-induced profile deterioration without the etch rate reduction in 3D NAND fabrication.

Vertical scaling technique faces a physical limitation in 3D NAND device fabrication, even assuming superior etching technology. Another promising scaling technique to increase the storage density is lateral scaling, which increases the number of holes between slit and slit from four to nine and above. However, unpredictable small critical dimension, feature-to-feature variation, and distortion occur. To elucidate the profile deteriorations induced by the lateral scaling, we analyzed the effect of the angular etching yield dependency of the incident ion fluxes into a given feature using the multiscale technology computer-aided design methodology. As one of the inherent features of the gas, incident angle θmax in which the sputtering yield achieves its maximum value is a crucial factor for analyzing and modeling etching profiles. Moreover, the impact of the heavy inert ion strikes on the unpreferred etching profiles was investigated. In this study, the synergy of lower energy ions, larger fluxes, and larger θmax of heavy inert ions decrease the feature-to-feature variation, reducing hard mask distortion without the etch rate reduction.

Cost-effective vertical etching of plug holes and word lines is crucial in enhancing 3D NAND device manufacturability. Even though multiscale technology computer-aided design (TCAD) methodology is suitable for effectively predicting etching processes and optimizing recipes, it is highly time-consuming. This article demonstrates that our deep learning platform called TCAD-augmented Generative Adversarial Network can reduce the computational load by 2 600 000 times. In addition, because well-calibrated TCAD data based on physical and chemical mutual reactions are used to train the platform, the etching profile can be predicted with the same accuracy as TCAD-only even when the actual experimental data are scarce. This platform opens up new applications, such as hot spot detection and mask layout optimization, in a chip-level area of 3D NAND fabrication.

Dielectric confinement (DC) effect is a phenomenon in which as the diameter of the silicon nanowire (SNW) decreases, the efficiency of dopant activation in silicon is reduced due to the dielectric surrounding the SNW. Inevitably, saddle-fin cell transistor for high density DRAM has silicon pillars like SNWs which are connected to storage capacitance and bit-line through polysilicon or silicon. In this paper, we implemented a dielectric confinement model in TCAD and fabricated saddle-fin cell arrays and specific test element groups for extracting resistance components using 20 nm technology node. It is found that the DC effect does not significantly affect the resistance values of storage node contact (SNC) and bit-line node contact (BLC) up to 20nm node, but becomes significant beyond sub 20nm node. The DC effect increases the variance of external resistance as well as the resistance value. This result indicates that it is necessary to find a proper solution to mitigate the DC effect, especially when using low-k materials to reduce the parasitic capacitance for sensing margin beyond sub 20nm technology node.

We propose a universal surface reaction model without any ad-hoc assumptions for fluorocarbon (FC) plasma oxide etching. A self-consistent numerical algorithm was developed to predict the deposition and etch yields simultaneously from our model considering the passivation layer and mixed layer. The internal model variables such as surface coverages showed consistent results under a wide range of FC plasma conditions. This model predicts the transition conditions between deposition and etch yield and the FC passivation layer thickness during the etching process. Finally, quantitative verification of the proposed model was performed through comparison to various FC plasma experimental data.

We propose a semi-global surface reaction model to capture simultaneous polymer deposition and oxide etching in fluorocarbon plasma. The critical parameters of this model within reasonable ranges can be determined using predesigned experimental data with plasma diagnostics in inductively coupled fluorocarbon plasma. This model can describe the transition behavior from polymer deposition to oxide etch self-consistently without ad-hoc assumptions, providing better insight into abnormal etching behaviors in high aspect ratio contact hole etching, such as sidewall bowing and twisting toward next generation of memory devices in semiconductor industries.

We have fabricated a recessed gate (RG) transistor for sense amplifier (SA) in high density DRAM and have compared it with a conventional planar gate (PG) transistor in terms of VT mismatch performance. The mismatch was reduced into 22% compared to PG and it was more superior at VT mismatch gap 86% between cold-hot temperature. It was attributed to the lower channel doping and the larger effective channel length in RG than PG. But RG showed phenomenon of randomly threshold voltage high flying in a few levels of 1K array, which makes VT mismatch of some RG transistors worse. In addition, the subthreshold swing (SS) of RG is inferior to that of PG. Failure analysis and TCAD modeling showed that the random VT high flying is caused by the Fermi-Level pinning at polysilicon gate grain boundaries, its effect increases only within a specific geometric angle range between grain boundary and channel surface and SS degradation comes from an electric field spreading at recessed channel corner, resulting in relatively low surface potential at channel corner than that of channel center. The above two phenomena were technically controlled and the industry's first RG technology was applied to SA transistor for highly scaled DRAM production.

We investigate the electrical characteristics according to changing temperature on trap distribution in the energy gap of grain boundary (GB) and interface trap density (D(it)) between polycrystalline-silicon (poly-Si) channel and tunnel oxide in Vertical NAND (VNAND) flash cell with poly-Si channel. We confirmed that there are two factors changing GB potential barrier height such as trap distribution in GB and D(it) using technology computer-aided design (TCAD) simulation. Also, we found that the electrical characteristics according to changing temperature are significantly dependent on height and position of GB potential barrier in VNAND flash cell with poly-Si channel. We expect that it is required to develop more accurate extraction method for trap distribution in each GB and D(it) for better understanding temperature dependence of electrical characteristics in VNAND Flash cell.

The influence of intercell trapped charge (ITC)-the charge trapped at the inter-cell nitride regions by fringe electric fields during programand erase operations-on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degradation mechanisms such as tunnel oxide damage, ITC deteriorates the transconductance and read current of VNAND flash memory cells. The influence of ITC-induced degradationon VNAND flashmemory is discussed, using both simulation and experimental results. A solution for ITC suppression is also proposed: the use of low-k intercell regions.

In this letter, a channel-stacked array with tied bit-line (BL) and ground select transistor (GST) is proposed to access each layer independently without additional string select transistors (SSTs) to a conventional planar NAND array. The proposed structure can maximize memory density, since additional SSTs are not required for layer selection and the placement of BLs/word lines is similar to that of the conventional NAND array except for island-type GSTs. Basic memory operations are performed with fabricated devices. The selected layer is erased only by applying erase voltage to the selected common source line (CSL) and by biasing inhibition voltage to other CSLs. Only the selected layer is read by applying the same voltage as BL voltage to the CSLs of the unselected layers. In addition, the selected strings in the selected layer are programmed and other strings in the selected and unselected layers are all inhibited by the combination of CSL and BL voltages. Consequently, stable memory operations are obtained successfully in the proposed structure without interference between stacked layers.

In this paper, we propose new string select transistors (SSTs)/dummy SSTs (DSSTs) threshold voltage (V th ) setting methods in simplified channel-stacked array with layer selection by multilevel operation (SLSM). In these methods, SSTs/DSSTs on each layer are set to their targeted V th values by incremental step pulse program/one erase with various erase voltages, respectively. In the fabricated pseudo-SLSM, the validity of the new methods is verified. As a result, it is confirmed that the V th values of SSTs/DSSTs are set to the targeted V th values by the new methods and SSTs with extremely narrow V th distribution can be obtained in the consequence. Moreover, memory operations such as erase, program, and read are performed in the fabricated structure after setting the V th values of all the SSTs/DSSTs by the new methods. Despite unique LSM operations, stable memory operations are obtained successfully without the interference between stacked layers.

A fast charge loss within a few seconds, which is referred to as early retention, was observed in tube-type 2y word-line stacked 3-D NAND flash memory for the first time, and the origin of the early retention was comprehensively evaluated. Using a fast-response pulse I-V system, the early retention characteristics from microseconds to seconds were thoroughly investigated, and the correlations with various program and erase levels were examined using solid and checkerboard patterns. Our findings indicate that the early retention mainly originates from the lateral charge loss through the shared charge trap layers and suggest that the program and erase levels should be balanced and optimized to reduce the early retention.

Program disturbance is analyzed in a simplified channel-stacked array with layer selection by multilevel operation after setting the threshold voltages (V-th) of string select transistors (SSTs)/dummy SSTs. There are additional unselected cells that should be inhibited in different ways, and they have the worse disturbance characteristics compared with conventional NAND arrays. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanism of the additional cases. It is found that initially nonprecharged channel and large leakage current flowing from channel to bitline degrade the disturbance. New program method is proposed along with low gate bias of dummy wordline. As a result, program disturbance is significantly improved and reliability is also enhanced by reducing the potential difference between the SST gate and the channel.

Retention characteristics of a 3-D NAND flash cell with tube-type poly-Si body are investigated at a high temperature (T) depending on program (P), neutral (N), and erase (E) states of adjacent cells. The trap density (Nt) in the nitride storage layer of the cell is extracted by utilizing retention model and deriving related equations in cylindrical coordinate. By programming or erasing adjacent cells, we can separate laterally distributed charge component from the retention characteristics. The adjacent cells which are programmed suppress significantly the lateral diffusion at a high T so that we can extract accurate Nt profile. Extracted peak of Nt at P-P-P mode is ~1.2×1019 cm-3eV-1 at an EC-ET of 1.0 eV. Retention characteristics with effective gate length and word-line biasing are also investigated.

We examine the utility of a generalised, non-Gaussian Karhunen-Loeve expansion in nuclear engineering applications. This is useful because in many situations the joint probability distribution function of the random variables of interest is unobtainable, whereas the marginals and covariance functions can generally be found. Given these priors, we follow and expand upon the work of other authors to transform the priors into a Gaussian covariance suitable for the Karhunen-Loeve expansion; this is done using the Nataf formulation which is explained in some detail. We derive analytical solutions to fundamental marginal distributions of the same and mixed types and show how the effective correlation function used in the K-L integral equation is related to the correlation function of the non-linear process. Specifically, we consider the uniform, step, triangular, Rayleigh, exponential, log-uniform and log-normal pdfs for covariance problems and the uniform + log-normal pdfs for a cross-covariance problem. We also show how these modified K-L expansions can be used to solve some simple neutron transport problems involving spatially stochastic cross sections with given probability distributions and associated correlation functions. An outcome of the investigation is a numerical study of the sensitivity of the final result, e.g. average flux and variance, to the Nataf transformation. That is whether it is always necessary to use this somewhat convoluted approach. In general, for problems in which the overall fluctuations are small it may not be necessary but one can often only decide this after a full Nataf calculation has been made, This aspect of the work is highlighted by our studies of transmission of neutral particles through a slab. (C) 2014 Elsevier Ltd. All rights reserved.

In this letter, we propose a simplified channel-stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage (V-th) setting method that all the SSTs on each layer are set to targeted the V-th values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAD simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the V-th values of SSTs are set to the targeted V-th values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the V-th values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub-10nm technology node.