Sub-Resolution Assist Feature (SRAF) printing is a critical yield detractor and known issue in OPC technology. SRAF print avoidance models can be used to determine where undesirable printing is likely to occur, but such models lack the necessary robustness and reliability for the detection of all SRAF printing cases. Classification of printing SRAFs is a subjective and manual task where many engineering hours are spent. In this work we demonstrate a reliable way to accurately classify images according to SRAF printing risk. Testing multiple sets of data, across multiple processes, yielded a prediction success rate of 97% wherein only a single image was under-predicted. Under-prediction is when a model fails to predict printing SRAFs; a key defect generator, as it means the model will not be able to remove the SRAF shape in the OPC iteration before mask build. We propose a new methodology as to accurately auto-classify and filter images with SRAF printing on wafer. This scalable solution will improve the quality and reliability of SRAF print avoidance models and reduce the risk of printing SRAF by removing the manual, highly subjective, image classification step.

State-of-the-art OPC recipes for production semiconductor manufacturing are fine-tuned, often artfully crafted parameter sets are designed to achieve design fidelity and maximum process window across the enormous variety of patterns in a given design level. In the typical technology lifecycle, the process for creating a recipe is iterative. In the initial stages, very little to no "real" design content is available for testing. Therefore, an engineer may start with the recipe from a previous node; adjust it based on known ground rules and a few test patterns and/or scaled designs, and then refine it based on hardware results. As the technology matures, more design content becomes available to refine the recipe, but it becomes more difficult to make major changes without significantly impacting the overall technology scope and schedule. The dearth of early design information is a major risk factor: unforeseen patterning difficulties (e.g. due to holes in design rules) are costly when caught late.To mitigate this risk, we propose an automated flow that is capable of producing large-scale realistic design content, and then optimizing the OPC recipe parameters to maximize the process window for this layout. The flow was tested with a triple-patterned 10nm node 1X metal level. First, design-rule clean layouts were produced with a tool called Layout Schema Generator (LSG). Next, the OPC recipe was optimized on these layouts, with a resulting reduction in the number of hotspots. For experimental validation, the layouts were placed on a test mask, and the predicted hotspots were compared with hardware data.

In this paper, we discuss the lithographic qualification of high transmission (High T) mask for Via and contact hole applications in 10nm node and beyond. First, the simulated MEEF and depth of focus (DoF) data are compared between the 6% and High T attnPSM masks with the transmission of High T mask blank varying from 12% to 20%. The 12% High T blank shows significantly better MEEF and larger DoF than those of 6% attnPSM mask blank, which are consistent with our wafer data. However, the simulations show no obvious advantage in MEEF and DoF when the blank transmittance is larger than 12%. From our wafer data, it has been seen that the common process window from High T mask is 40nm bigger than that from the 6% attnPSM mask. In the elongated bar structure with smaller aspect ratio, 1.26, the 12% High T mask shows significantly less develop CD pull back in the major direction. Compared to the High T mask, the optimized new illumination condition for 6% attnPSM shows limited improvement in MEEF and the DoF through pitch. In addition, by using the High T mask blank, we have also investigated the SRAF printing, side lobe printing and the resist profile through cross sections, and no patterning risk has been found for manufacturing. As part of this work new 12% High T mask blank materials and processes were developed, and a brief overview of key mask technology development results have been shared. Overall, it is concluded that the High T mask, 12% transmission, provides the most robust and extendable lithographic solution for 10nm node and beyond.

The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process. (C) 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)

Continued improvements in SEM contour extraction capabilities have enabled calibrating more accurate OPC models for advanced technology nodes using a hybrid approach, combining CDs for 1D structures and full contour measurements for more complex 2D patterns. Previous work has addressed various components of contour modeling including alignment, edge detection, CD to contour consistency, and image parameter space coverage. This study covers weighting strategies for CDs compared to contours. Additionally the total number of structures in a sample plan can be reduced by incorporating contours for model calibration due to the increased number of evaluation points they provide. Repeated measurements of the same structure at separate locations are used to extract SEM contours across several instances. The average measurements from these locations can then be used for OPC model calibration. Using 14nm process data, it is shown that including more contours in hybrid OPC model calibration leads to improved model verification. Within an appropriate range, higher weight on the contour patterns leads to improved model verification on measurement sites unseen by the calibration set. Calibrating a model with fewer contour structures, but at higher weight shows improvement over standard CD only model calibration.

Extreme ultraviolet lithography (EUV) advances printability of small size features for both memory and logic semiconductor devices. It promises to bring relief to the semiconductor manufacturing industry, removing the need for multiple masks in rendering a single design layer on wafer. However, EUV also brings new challenges, one of which is of mask defectivity. For this purpose, much of the focus in recent years has been in finding ways to adequately detect, characterize, and reduce defects on both EUV blanks and patterned masks. In this paper we will present an efficient way to classify and disposition EUV mask defects through a new algorithm developed to classify defects located on EUV photomasks. By processing scanning electronmicroscopy images (SEM) of small regions of a photomask, we extract highdimensional local features Histograms of Oriented Gradients (HOG). Local features represent image contents compactly for detection or classification, without requiring image segmentation. Using these HOGs, a supervised classification method is applied which allows differentiating between nondefective and defective images. In the new approach we have developed a superior method of detection and classification of defects, using mask and supporting mask printed data from several metallization masks. We will demonstrate that use of the HOG method allows realtime identification of defects on EUV masks regardless of geometry or construct. The defects identified by this classifier are further divided into subclasses for mask defect disposition: foreign material, foreign material from previous step, and topological defects. The goal of disposition is to categorize on the images into subcategories and provide recommendation of prescriptive actions to avoid impact on the wafer yield.

Hybrid OPC modeling is investigated using both CDs from 1D and simple 2D structures and contours extracted from complex 2D structures, which are obtained by a Critical Dimension-Scanning Electron Microscope (CD-SEM). Recent studies have addressed some of key issues needed for the implementation of contour extraction, including an edge detection algorithm consistent with conventional CD measurements, contour averaging and contour alignment. Firstly, pattern contours obtained from CD-SEM images were used to complement traditional site driven CD metrology for the calibration of OPC models for both metal and contact layers of 10 nm-node logic device, developed in Albany Nano-Tech. The accuracy of hybrid OPC model was compared with that of conventional OPC model, which was created with only CD data.Accuracy of the model, defined as total error root-mean-square (RMS), was improved by 23% with the use of hybrid OPC modeling for contact layer and 18% for metal layer, respectively. Pattern specific benefit of hybrid modeling was also examined.Resist shrink correction was applied to contours extracted from CD-SEM images in order to improve accuracy of the contours, and shrink corrected contours were used for OPC modeling. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total error RMS was decreased by 0.2nm (12%) with shrink correction technique. Variation of model accuracy among 8 modeling runs with different model calibration patterns was reduced by applying shrink correction. The shrink correction of contours can improve accuracy and stability of OPC model.

The need to quickly and flexibly characterize the design manufacturability increases as circuit design scales beyond the 22nm node. Improvements in design practices and design software are enabling this process. The use of carefully characterized design subunits (cells) in the general assembly of the chip is one way to ensure that products are optimized for these increasingly difficult lithographic process challenges. Additionally, software for assessing design robustness has been enhanced to deal with ever more complex resolution enhancement techniques. State of the art simulator and verification tool sets provide the necessary step of creating simulation contours and process variability bands upon which various checks can then be performed. The construction of these contours and bands is often hidden from the user as traditional single or double exposure processes of one or two masks are assumed to be used to create the final layout pattern.With the introduction of many different process techniques that include double or multiple patterning steps, such traditional assumptions are no longer valid. A new mechanism needs to be implemented that supports any type and combination of patterning processes in a simple yet accurate fashion to construct the process variability bands that will be used for verification of the pattern manufacturability of the layout. To address these concerns a new Black Box Interface (BBAPI) has been introduced that allows process teams to customize the generation of process variability objects to reflect the specific manufacturing steps of the Fab, without losing the data encapsulation needed to protect the process' intellectual property while maintaining the usability of litho friendly design (LFD) concepts during physical synthesis.The increased flexibility in creating contours and bands ultimately leads to more robust physical designs which are aware of every part of the patterning process. This paper describes the design and co-optimization techniques including: optimization of base technology (P-cell) constructs, choice of base technology constructs in IP cell design, and a new application program interface (API) to simulation tools. The paper demonstrates an optimized design process integrating techniques to improve design stability and ease of assembly of robust chip designs for advanced optical process technologies.

For process development of deep-subwavelength technologies, it has become accepted practice to use model-based simulation to predict systematic and parametric failures. Increasingly, these techniques are being used by designers to ensure layout manufacturability, as an alternative to, or complement to, restrictive design rules. The benefit of model-based simulation tools in the design environment is that manufacturability problems are addressed in a design-aware way by making appropriate trade-offs, e.g., between overall chip density and manufacturing cost and yield. The paper shows how library elements and the full ASIC design flow benefit from eliminating hot spots and improving design robustness early in the design cycle. It demonstrates a path to yield optimization and first time right designs implemented in leading edge technologies. The approach described herein identifies those areas in the design that could benefit from being fixed early, leading to design updates and avoiding later design churn by careful selection of design sensitivities. This paper shows how to achieve this goal by using simulation tools incorporating various models from sparse to rigorously physical, pattern detection and pattern matching, checking and validating failure thresholds.

Optimization of semiconductor product yield requires control of systematic defects. A variety of industry tools are available to check designs for systematic layouts that will be difficult to manufacture. Because of the cost associated with setting up the rules for a checking tool and the cost of licenses needed to evaluate designs, manufacturing process lines typically enable a limited set of tools to evaluate designs for systematic yield sensitivity. Semiconductor product design systems typically incorporate library elements designed by third party design companies. When third party library suppliers do not have access to the licenses or expertise to use the tools selected by the target manufacturing line, a barrier is created to having all library elements in a semiconductor design system checked to the same level. This results in a yield exposure for library elements that are not evaluated and fixed. This paper describes a method used to enable systematic yield evaluation for 32nm library elements procured from third party library suppliers. The third party library supplier provides layout data to the contracting library owner for yield sensitivity analysis. Changes are prioritized and fed back to the third party library supplier. This method interlocks design practices with the third party library supplier and provides a means for the contracting library owner to evaluate third party library elements and provide feedback to optimize the design.

As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.