According to Heisenberg’s uncertainty principle, measurement of a quantum observable introduces noise to this observable and thus limits the available precision of measurement. Quantum non-demolition measurements are designed to circumvent this limitation and have been demonstrated in detecting the photon flux of classical light beam. Quantum non-demolition measurement of a single photon is the ultimate goal because it is of great interest in fundamental physics and also a powerful tool for applications in quantum information processing. This chapter presents a brief introduction of the history and a review of the progress in quantum non-demolition measurement of light. In particular, a detailed description is presented for two works toward cavity-free schemes of quantum non-demolition measurement of single photons. Afterward, an outlook of the future in this direction is given.

A transmission line induced skew reduction system for shutter signals of a pixel array has been designed using TowerJazz CIS 0.18m technology. It is based on the use of multiple delay-locked loop in charge of close-to-close synchronization. The simulation results demonstrate the ability of the system to compensate the transmission line induced skew from 1.58ns to 75ps. The measurements made with a prototype integrating a 11.6mm servo-controlled transmission line and fours delay-locked loop demonstrated a reduction of its skew down to 32ps.

Time-correlated single-photon counting (TCSPC) applications usually deal with a high counting rate, which leads to a decrease in the system efficiency. This problem is further complicated due to the random nature of photon arrivals making it harder to avoid counting loss as the system is busy dealing with previous arrivals. In order to increase the rate of detected photons and improve the signal quality, many parallelized structures and imaging arrays have been reported, but this trend leads to an increased data bottleneck requiring complex readout circuitry and the use of very high output frequencies. In this paper, we present simple solutions that allow the improvement of signal-to-noise ratio (SNR) as well as the mitigation of counting loss through a parallelized TCSPC architecture and the use of an embedded memory block. These solutions are presented, and their impact is demonstrated by means of behavioral and mathematical modeling potentially allowing a maximum signal-to-noise ratio improvement of 20 dB and a system efficiency as high as 90% without the need for extremely high readout frequencies.

The real time acquisition of a 3D scene has been recently democratized by video game consoles. The most popular approaches such as the structure-light and the stereo vision are appropriate for short distances but they are not well suited for long time measurements in the range of a hundred meters up to a few kilometers or a scattering environment. In this case, the time of flight method is more convenient but is limited by the heavy and expensive hardware requirement for military applications. Indeed, a strong laser illumination and a time gated intensified camera is generally used to carry out this kind of measurement. The signal reflected at a long distance is so weak that very few photons reach the camera, thus using an image intensifier is mandatory. Moreover, the acquisition time and processing is quite long as several laser pulse are required for distance measurement and several frame of distance measurement are required to build a 3D scene. As a consequence, real time measurement cannot be achieved at this time. The paper describes a novel CMOS imager based on time gated single photon avalanche diode in order to detect the reflected light and accomplish distance memorization. The processing is fully parallelized and embedded within the pixel. The pixel includes 46 transistors, operates independently and has a size of 36×43 μm 2 . As a result, the readout of the sensor generates the 3D images immediately in real time.

This paper presents the simulations and characterizations results of a hybrid Time to Digital Converter (TDC) fabricated in 180 nm standard CMOS. The design combines the traditional Analog Time to Amplitude Converter (TAC) and Digital TDC techniques to obtain a high adjustable time precision. These approach leads to a 3 bits enhancement of the least significant bit resolution (LSB) for the proposed design. The characterization results showed a time precision of 10 ps with an estimated INL of 5.6 ps rms for a 2.5 ns reference period clock and a 32 cells delay line loop.

We present the performance characteristics of a single photon avalanche diode (SPAD) fabricated in a 180 nm standard CMOS image sensor technology. The SPAD structure was implemented in 8 different diameters between 5 and 40 μm to determine the influence of size variation on the SPAD performances in terms of dark count rate, afterpulsing, efficiency and time resolution. The measurements show a dark count rate below 10 kHz at 15 °C with a low afterpulsing probability (0.2 % at an excess bias of 300 mV), a good Photodetection efficiency (~20 %) and a very good time resolution (<70 ps FWHM at 450 nm) .

This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets. First, the paper illustrates how to take advantage of the presence of carry chains in elementary logic elements of the FPGA in order to enhance the TDC resolution. Then, it describes how to use the Chip Planner tool to place the partitions composing the system in user specified physical regions. This allows the placement of TDC partitions so that the routing paths are constrained. As a result, the user controls the propagation delay effectively through the connection network. The paper ends by applying the presented methodology to a case study showing the design and implementation of high resolution TDC dedicated to time correlated single photon counting system. The resolution of 42 ps as well as the INL, DNL and mean Jitter values (22 ps rms, 13 ps rms and 26 ps rms, respectively) obtained using a low cost FPGA target Cyclone family are very promising and suitable for a large amount of fast applications.

We present the performance characteristics of a Single Photon Avalanche Detector fabricated in a 180 nm standard CMOS image sensor technology. The SPAD implemented in 8 different diameters between 5 μm and 40 μm shows a DCR below 10 kHz at 15°C with a low afterpulsing probability (0.2% at 300 mV), a good photodetection efficiency (20%) and a very good time resolution (80 ps at 450 nm).

This work is dedicated to show the impact of integrating an embedded FIFO in a TCSPC system on the counting loss probability for a given expected arrival rate to an output rate frequency. To do this we used an M/D/1/N queuing model which is applied to design a multichannel TCSPC system. The results show that associating a FIFO to a multichannel system allows increasing the efficiency up to 90% while the standalone multichannel system one's is only of about 54%.

— This work aims to introduce a design methodology of Time-to-Digital Converters (TDCs) on low cost Field-Programmable Gate Array (FPGA) targets. First, the paper illustrates how to take advantage of the presence of carry chains in elementary logic elements of the FPGA in order to enhance the TDC resolution. Then, it describes how to use the Chip Planner tool to place the partitions composing the system in user specified physical regions. This allows the placement of TDC partitions so that the routing paths are constrained. As a result, the user controls the propagation delay effectively through the connection network. The paper ends by applying the presented methodology to a case study showing the design and implementation of high resolution TDC dedicated to fast imaging systems. The obtained resolution of 42 ps using a low cost FPGA target Cyclone family is very promising and suitable for a large amount of fast applications.

This paper presents a new Time to Digital Converter (TDC) design that combines the traditional Analog Time to Amplitude Converter (TAC) and Digital TDC techniques to obtain a very high adjustable time precision that could reach 10ps with a maximum dynamic range of 10 μs a DNL of 0.4 LSB a dead time of 15 ns. The proposed new “hybrid TDC” concept was used to design an array of 8 time interval measurement units for a Time correlated single photon counting(TCSPC) system in a 0.18 μm CMOS technology. The common Delay locked loop (DLL) and coarse counter approach makes the design flexible and easily scalable allowing the conception of larger TDC arrays without the need to implement several DLLs.

A Macropixel for photon counting integrated streak camera has been developed in a 180nm standard CMOS process. It includes a 4×4 array of Single Photon Avalanche Diodes (SPAD) acting as a small and smart SiPM (Silicon Photo Multiplier), a unique quenching circuit and a 16 bits memory for smart pixel operation. The total Macropixel size is 32×314 μm2, with a sensitive area size of 32×32 μm2. The SPAD pitch of 8 μm makes possible to use the standard micro-lens option proposed by the image sensor process and thus to increase the fill factor from the actual 7% up to nearly 100%. Thanks to the embedded memory, each SPAD can be individually enabled or disabled in order to reduce the dark count rate and consequently improve the signal to noise ratio.

Several works have demonstrated the successfully integration of Single-photon avalanche photodiodes (SPADs) operating in Geiger mode in a standard CMOS circuit for the last 10 years. These devices offer an exceptional temporal resolution as well as a very good optical sensitivity. Nevertheless, it is difficult to predict the expected performances of such a device. Indeed, for a similar structure of SPAD, some parameter values can differ by two orders of magnitude from a technology to another. We proposed here a procedure to identify in just one or two runs the optimal structure of SPAD available for a given technology. A circuit with an array of 64 SPAD has been realized in the Tower-Jazz 0.18 mu m CMOS image sensor process. It encompasses an array of 8 different structures of SPAD reproduced in 8 diameters in the range from 5 mu m up to 40 mu m. According to the SPAD structures, efficient shallow trench insulator and/or P-Well guard ring are used for preventing edge breakdown. Low dark count rate of about 100 Hz are expected thanks to the use of buried n-well layer and a high resistivity substrate. Each photodiode is embedded in a pixel which includes a versatile quenching circuitry and an analog output of its cathode voltage. The quenching system is configurable in four operation modes; the SPAD is disabled, the quenching is completely passive, the reset of the photodiode is active and the quenching is fully active. The architecture of the array makes possible the characterization of every single photodiode individually. The parameters to be measured for a SPAD are the breakdown avalanche voltage, the dark count rate, the dead time, the timing jitter, the photon detection probability and the after-pulsing rate.