To provide good classification accuracy and meet challenging design constraints, image classifiers deployed in embedded systems are typically implemented using convolutional neural networks (CNNs) accelerated with specialized inference accelerators. We propose a supernet-based neural architecture search (NAS) method to automate the design process of CNNs executed on the Hailo-8L accelerator, an expanding module for the Raspberry Pi Kit. The method utilizes a multi-objective genetic algorithm in conjunction with a pre-trained supernet and latency predictor to accelerate the evaluation of candidate CNNs. The latency predictor is trained using a collection of generated CNNs whose exact latency is determined directly on the Hailo-8L accelerator. The method is evaluated using CIFAR-100 and ImageNet-100 benchmarks and provides classifiers with competitive accuracy-latency trade-offs.
Field-programmable gate arrays (FPGAs) are widely adopted as accelerators for compute-intensive applications. In modern FPGA flows, floorplanning provides coarse-grained region constraints, but commercial tools offer no automatic support, requiring designers to manually define partition regions that substantially impact placement and routing. This paper presents a fully automatic framework that generates resource-guided floorplanning constraints to improve the clock frequency of FPGA designs. The framework employs a divide-and-conquer strategy with nonlinear optimization for resource-aware region assignment, exploiting FPGA heterogeneity in a device-agnostic manner and producing constraints that integrate into commercial toolflows. The framework has been integrated into Vivado and tested with nine benchmarks and two platforms, improving the maximum clock frequency by 11.4
As computing needs are expanding, scaling up the general-purpose computing resources is limited by energy consumption and efficiency. Coarse-Grained Reconfigurable Arrays (CGRAs) are a solution to that challenge: they are versatile digital architectures, capable of achieving near-ASIC level of energy efficiency without sacrificing reconfigurability. However, CGRAs are limited to the instructions they were built with. Unsupported operations must be emulated, which severely impacts performance. To preserve CGRAs inherent features while enabling higher reprogrammability, we propose MultiGRA: an architecture template that expands the fixed CGRA’s instruction set by including embedded FPGA fabrics (eFPGA) inside the CGRA as finely reconfigurable zones. The eFPGA areas are capable of implementing application-specific operators, specialized at compilation time. This approach avoids overprovisioning computing resources, since the architecture can be freely retargeted. We investigate two of the many integration possibilities of eFPGAs in CGRAs with the respective gains. Examples of post-synthesis ASIC area measurements are provided to show integration feasibility. In a case study comparing CGRAs and MultiGRAs, MultiGRAs show up to 40
Pre-trained language models (LMs) deliver strong performance across a wide range of Natural Language Processing (NLP) tasks but remain costly to deploy on embedded devices due to their high memory and compute requirements. A widely used strategy for adapting LMs to resource-constrained devices is aggressive quantization. At low bit-widths, mixed-precision schemes, where different components of the model use different numerical precisions, offer an effective balance between compression and accuracy. In this work, we evaluate the impact of mixed-precision quantization for inference on the BERT language model. Unlike prior studies that often overlook activation quantization, our evaluation systematically explores mixed-precision configurations for both weights and activations. We also examine the effects of quantizing the embedding layer, which is commonly limited to token-weight quantization. Evaluated on the SQuAD and GLUE benchmarks, our approach achieves substantial reductions in memory and computational cost without sacrificing accuracy.
The growing demand for secure healthcare services in medical IoT networks has raised the need for robust anomaly detection systems, with autoencoder (AE) as a compelling solution. Although mapping of neural networks on FPGAs is well-known, selecting a suitable High-Level Synthesis (HLS) framework for a particular use case remains a challenge. This work explores the trade-offs between two well-known, open-source HLS frameworks: hls4ml and FINN by evaluating non-functional metrics for deploying AEs. Our results highlight that hls4ml achieves roughly 10× lower latency and 3× higher throughput as compared to FINN. On the other hand, FINN provides a comprehensive, automated end-to-end solution for deploying quantized networks on FPGA with up to 80
Outsourcing accelerates AI hardware development but exposes designs to hardware Trojan (HT) risks. The stealthy nature of HTs and increasing complexity of CNN accelerators limit the effectiveness of traditional detection and localization techniques. This paper presents a segmentation-driven power side-channel framework combined with a customized BERT-inspired model to localize HT-affected regions relative to a trusted baseline. By dividing traces into segments and analyzing them with transformer attention, the method enables targeted auditing and reduces manual inspection. Experiments on real power measurements with physical HTs achieve 92.1
The performance of deep learning models is heavily coupled to hardware, with SIMT-based GPUs being the de facto standard. Novel architectures like the Graphcore Intelligent Processing Unit (IPU), with its Multiple Instruction, Multiple Data (MIMD) design and distributed on-chip SRAM, offer a different paradigm. However, direct performance comparisons for complex, state-of-the-art computer vision models are sparse. This paper presents a comprehensive performance benchmark of the Scaled-YOLOv4-P5 object detection model on a Graphcore GC200 IPU against a comparable NVIDIA A30 GPU. We investigate the performance trade-offs by analyzing inference latency and throughput while varying image size, batch size, and floating-point precision. Our findings reveal a stark performance trade-off. The IPU excels in low-latency scenarios, delivering a 6.56 ms inference time at batch=1 (896 px), nearly 4x faster than the GPU’s 26.17 ms. Conversely, the GPU’s SIMT architecture scales near-linearly for high-throughput, while the IPU is severely memory-constrained. The IPU failed to compile at batch=2 for the native 896px resolution, limited by its ∼ 900 MB on-chip SRAM. In contrast, the GPU’s 24 GiB HBM2 memory handled batches of ≥ 64 at the same resolution. Furthermore, the IPU’s Ahead-of-Time compilation incurs a major overhead: a full benchmark run at 896 px took 382.79 s on the IPU versus just 15.56 s on the GPU, with 75–88
To achieve further performance and efficiency, System-onChip (SoC) designs increasingly rely on core customization or integration of application-specific hardware blocks. This requires extensive efforts during Design Space Exploration (DSE) of new hardware to achieve integration, correctness, and target performance. This is time-consuming and error-prone, hindering fast iterative hardware/software co-design. This paper presents a co-simulation framework which integrates arbitrary high-level simulators into Verilog-based SoC platforms, demonstrated on the RISC-V–based open-source X-HEEP SoC. Using inter-process communication we enable cycle-accurate lock-step co-simulation where high-level simulators of accelerators are exposed as memory-mapped peripherals to the RISC-V core. For experimental validation we re-implemented an existing peripheral of the X-HEEP SoC written in Register-Transfer Level (RTL) as an external simulator process, and observed that the co-simulated version maintains identical cycle-level behavior with a maximum wall-clock overhead of 11
The rapid progression of Artificial Intelligence has made Vision Transformers (ViTs) crucial for computer vision, offering accuracy comparable to or exceeding that of CNNs. However, ViTs present implementation challenges on hardware platforms, requiring the processing of larger matrices, leading to substantial parameter counts and demanding memory accesses. In response to these challenges, this paper introduces a Configurable Matrix Multiplication Module C3M-ViT. It employs a highly parallel temporal structure based on clusters of Processing Elements (PEs) organized in a two-dimensional matrix. By leveraging a tiling methodology and an optimized dataflow, the C3M-ViT achieves efficient storage without the need for data rearrangement enabling uniform handling of both input and output layers, while maintaining a high PE utilization rate. Furthermore, the C3M-ViT’s weight loading strategy significantly reduces memory footprint by eliminating the necessity to store entire weight matrices. This paper present a 5 × 4 cluster matrix configuration with 1,446 parallel PEs, delivering 77.6 GOPs/W energy efficiency, which is approximately three times higher than comparable state-of-the-art accelerators under similar conditions.
This paper presents a novel approach to ultra-low latency implementation of Sigma Delta (SD) Digital-to-Analog Converters (DACs) on Field Programmable Gate Arrays (FPGAs). We detail the design, simulations, and VHDL implementation of the proposed SD DACs. The paper provides an approach for a design-space exploration to find a tradeoff between the internal word lengths of calculations in the DAC and the Signal to Noise Ratio (SNR) of the output audio signal. In simulations, the proposed DAC can achieve an SNR of approximately 170 dB for input sample rates of 48 kHz - 768 kHz with the IP running at 49.152 MHz, resulting in an Oversampling Ratio (OSR) of 1024 - 64. In measurements, the DAC provides a latency inferior to 1 s. Our SD DAC implementation has been integrated as an IP core to the SyFaLa toolchain, which aims to facilitate the prototyping of real-time audio Digital Signal Processing (DSP) applications on FPGA.
Evaluating non-functional properties such as power consumption on microcontroller platforms exposes a gap between abstraction layers: while programs execute at the Instruction Set Architecture (ISA) level, energy consumption is determined at the circuit level. This connection between system and circuit layers is especially relevant when modeling non-functional processor properties. Modern approaches (e.g., deep neural networks) rely on large datasets, which in turn require automated methods that generate consistent labelling between programs and their measured energy consumption and latency. We introduce an open-source, automated framework that applies a measurement-based approach for energy consumption and latency characterization. The framework allows users to treat hardware as a physical black box while still obtaining measurements of instruction sequences, even without performance counters or integrated power-monitoring infrastructure. The system is built entirely from low-cost commercial off-the-shelf (COTS) components. It relies on repeated measurement cycles, averaging many iterations of the same program under test. Each cycle includes a state-flush routine, which executes code intending to reset the microarchitectural state to capture state-dependent effects. Preliminary experiments on two RISC-V platforms (ESP32-C6 and BananaPi BPi-F3) reveal that some of the tested state-flush methods introduce a high degree of unwanted noise, especially for energy measurements.
The design and validation of security architectures for Unmanned Aerial Vehicle (UAV) swarms, such as on-board Intrusion Detection Systems (IDS), require simulation platforms that can rapidly prototype complex cyber-physical scenarios. These platforms must simultaneously capture accurate flight dynamics and realistic network behavior while remaining scalable and reproducible. This paper introduces Unmanned Aerial Vehicle Link and Queue (UAVLnQ), an open-source architecture explicitly designed to address these challenges. It integrates ArduPilot Software-in-the-Loop (SITL) with ns-3 through a ZMQ middleware that guarantees synchronization between mobility control and packet-level events. UAVLnQ features an autopilot mission control system for defining and executing complex swarm behaviors. We demonstrate its capabilities in a leader-follower formation under representative cyber-attacks—including command injection, spoofing, and denial of service—providing a validated environment for the development and testing of novel security and resilience solutions. UAVLnQ thus establishes itself as a reproducible and extensible foundation for a new generation of UAV swarm networking and cyber-defense research.
Dynamically reconfigurable hardware offers significant adap- tability and performance advantages for modern System-on-Chip (SoC) architectures, but also enlarges the system’s attack surface. Previous work has shown that reconfigurable accelerators can exploit weaknesses in Input Output Memory Management Unit (IOMMU) to perform unauthorized Direct Memory Accesss (DMAs), revealing limitations in current I/O protection mechanisms. This paper presents ARMOR, a hardware mechanism designed to ensure the trustworthy integration of reconfigurable accelerators within IOMMU-enabled SoCs. ARMOR enforces secure device identity verification and provides runtime supervision of accelerator activity to detect and prevent abnormal or malicious behavior. Implemented in a RISC-V environment and validated through simulation, it effectively prevents I/O-based attacks while maintaining system compatibility and low performance overhead.
This work evaluates State-of-the-Art convolution algorithms for CPU-based CNN inference. Although most prior studies focus on GPUs or NPUs, CPU implementations remain comparatively under-optimized. Our first contribution is to provide fair benchmarking for embedded CPU inference. We evaluate direct, GEMM-based, and Winograd convolutions across modern CPUs from ARM®, Intel®, AMD®, and NVIDIA® vendors, considering both latency and energy efficiency. To the best of our knowledge, this is the first study to present a fair, cross-vendor comparison of CPU energy consumption using a high-resolution socket-level measurement platform. To validate our methodology, we further compare socket-level power measurements with estimates derived from model-specific registers (MSRs), finding that MSRs underestimate the power consumption of convolution inference by 10–30
Fault injection attacks exploit physical disturbances to compromise the functionality and security of integrated circuits. As System-on-Chip (SoC) architectures grow in complexity, the vulnerability of on-chip communication buses has become increasingly prominent. Buses, serving as interconnects among various IP cores, represent potential attack vectors for fault-based exploitation. In this study, we perform simulation-driven fault attack injection across three mainstream bus protocols— Wishbone, AXI-Lite, and AXI. We systematically examine fault attack success rates, spatial vulnerability distributions, and timing dependencies to characterize how faults interact with bus-level transactions. The results uncover consistent behavioral patterns across protocols, offering practical insights for both attack modeling and the development of resilient SoC designs.
In the field of Deep Learning, the high number of parameters in models has become a significant concern within the scientific community due to the increased computational resources and memory required for training and inference. Addressing this issue, we propose a novel tensorized technique to compress network architectures. Our approach aims to significantly reduce the network's size and the number of parameters by integrating Averaged Higher Order Singular Value Decomposition with a novel Knowledge Distillation approach. Specifically, we replace certain layers of the original architecture with layers that perform linear projections onto a reduced space defined by our reduction technique. We conducted experiments on image classification tasks using multiple architectures and datasets. The evaluation focuses on final accuracy, model size, and parameter reduction, comparing our approach with both the original models and quantization, a widely used reduction method. The results underscore the effectiveness of our method in significantly reducing the number of parameters and the overall size of neural networks while maintaining high performance.
Low Density Parity Check (LDPC) codes under iterative decoding have shown remarkable error correction capabilities, with moderate complexity requirements. Initially, in this paper a check based on a part of the parity check matrix (core part check) is presented. The proposed check is amenable for hardware implementation and allows the termination of the decoding procedure at a sub-iteration level, i.e., within an iteration. In this way the number of clock cycles required reduced by 150 for the semi-parallel architecture and for 5G NR codes. Simultaneously the Block Error Rate (BLER) remains the same while hardware becomes simpler. In addition, this paper introduces a novel scheduling scheme combined with the core part check and a syndrome-select logic. Experimental results are offered, assuming the parallel architecture, which show that the proposed rescheduling reduces the average number of required clock cycles per decoded word. Simultaneously improves the BLER utilizing exactly the same hardware. Specifically, targeting 5G NR LDPC codes, gains of 35
Underwater imaging presents unique challenges compared to open-air photography, primarily due to diminished visibility and geometric distortions, impeding the development of underwater Computer Vision (CV) and robotic vision perception. Previous methods relying on simplified image formation models for image enhancement have often yielded unsatisfactory results. This paper proposes a new deep learningbased architecture for joint depth estimation and dehazing from a single underwater monocular image, seeking to take advantage of the mutual benefits between these two interrelated tasks. The proposed architecture is a Two-Headed Depth Estimation and Dehazing Attention Network (2HDED:AttN) with an end-to-end training approach. Comprehensive experiments on synthetic and real underwater datasets showcase the proposed architecture's superior performance in jointly addressing underwater depth estimation and image dehazing tasks. The method effectively estimates underwater depth and improves underwater image quality, paving the way for enhanced underwater computer and robotic vision applications.
This paper introduces a synthesizable -architectural design method to boost the performance of a given RISC-V processor architecture by utilizing Canonical Signed Digit (CSD) representation during the execution stage within the processor pipeline. CSD is a unique ternary number system that enables carry/borrow-free addition/subtraction in constant time O(1) regardless of word length N. The CSD extension is exemplarily demonstrated to the Potato processor, a simple RISC-V implementation for FPGAs. However, the method can also be applied to other implementations in principle. Our performance boost due to the CSD requires an overhead for conversion between binary and CSD representation. This overhead is compensated by an extension to a seven-stage pipeline architecture, featuring a three-step execution stage that increases the throughput and the operating frequency and enables loop unrolling, which is especially advantageous in applications with consecutive calculations, e.g., signal processing. By experimental results, we compared our CSD-based ternary solution to the original implementation, which utilizes the usual pure binary number representation of the operands. Our approach achieved a 2.41X increase in operating frequency over the original RISC-V processor on FPGA, with over 20
Efficient memory management is essential for signal and image processing systems, particularly in data-intensive applications where performance and resource constraints are critical. This paper presents a comparative study of two advanced memory optimization techniques: Memory Script Optimization (MSO), and Passive Active Flow Graph (PAFG) Optimization-within the context of dataflow-modeled applications. Both approaches aim to reduce memory usage and improve execution efficiency, but they do so with distinct strategies: Memory Scripts focus on in-place buffer management, while PAFG modifies actor interactions to minimize buffer requirements. Using a portion of a Convolutional neural network (CNN) application as a case study, we evaluate the efficiency of these techniques in terms of memory reduction and execution time. Our results demonstrate that MSO provides significant performance improvements, achieving up to 17
