Bluetooth Low Energy (BLE) mesh networks enable diverse communication for the Internet of Things (IoT). However, existing BLE mesh implementations cannot simultaneously achieve low-power operation, symmetrical communication, and scalability. A major limitation of mesh networks is the inability of the BLE stack to handle network-scalable time synchronization. Pulse-coupled oscillators (PCOs) have been studied extensively and are able to achieve fast and reliable synchronization across a range of applications and network topologies. This paper presents a lightweight physical (PHY) layer accelerator to the BLE stack that enables scalable synchronization command with a PCO. The accelerator is a fully digital solution that can be synthesized with only the standard cells available in any silicon technology. This paper provides a detailed analysis of PCO-based BLE mesh networks and explores per-node system-level requirements. Finally, the analytical results are validated with measurements of a custom radio node based on the ubiquitous AD9364 transceiver.

We present a hardware accelerator, fabricated in 180 nm CMOS, for baseband timing of BLE mesh networks. The timing circuitry augments the BLE physical layer with a new command that enables scalable synchronization and aggressive duty-cycling of mesh nodes for low-power P2P communication. The custom ASIC contains a digital correlator which enables low-latency detection of a BPSK synchronization packet, or syncword. The detected syncword advances the phase of a nonlinear pulse-coupled oscillator, which drives the network to a synchronized state. The accelerator interfaces with the AD9364 software-defined radio via a ZedBoard to make a fully functional node. Duty-cycled multi-hop communication is demonstrated with total power consumption per radio node of less than 1 mW while communicating 64-bit 10 MSPS packets.

We present a network of dynamic capacitance sharing (DCS) switched-capacitor converters that increase the range of efficient voltage regulation for multiple independent loads while reducing area overhead. Since maximum power dissipation is fixed for a single chip due to thermal constraints, the proposed converters consider the overall power budget of multiple voltage-scalable loads to dynamically share energy storage area, allowing the dynamic allocation of energy storage clusters on-demand. Our DCS converters utilize a feedback control scheme including both capacitance and frequency modulation, which leads to the order of 10-100ns voltage settling times. A test chip with 16 clusters and four regulator control loops is fabricated in 65-nm bulk CMOS process. For a 2.3V input, our DCS converters achieve 0.742V at 38.1mA to 1.367V at 298mA output with peak efficiency of 70.9% at 550-mW/mm(2) power density. Regulator area for the four-load network is reduced by up to 70% when operating under a power constraint compared with the stand-alone per-load regulators capable of supporting an equivalent range of operating voltages.

Silicon prototyping has historically played a key role in computer architecture research by validating assumptions, enabling measurement of real system-level performance and energy efficiency, and grounding simulation-based studies. The demand for silicon prototyping has risen dramatically due to a surge in hardware innovation driven by fast-paced advances in software (e.g., machine learning applications). Silicon prototyping in this climate further provides critical answers to business concerns including estimated total cost of ownership and product/market fit. However, in conventional wisdom, building chips is a massive undertaking that is simply out of reach for most researchers. In this paper, we argue that advancements in open-source infrastructure for the RISC-V ecosystem are synergizing with continued development of productive open-source design tools to significantly reduce design challenges. At the same time, multi-project wafer services have begun supporting advanced technology nodes with very small minimum sizes for significantly reduced costs, bringing forth a new era of silicon prototyping in which anyone can build prototypes. This paper provides a case study for cost-effective and productive silicon prototyping and describes how we paired the RISC-V ecosystem with productive open-source design tools to build a small 1⇥1.25 mm RISC-V system in TSMC 28 nm. The prototype is written in an open-source Python-based hardware modeling language, includes a fully synthesizable PLL written in SystemVerilog, and was built with an open-source modular VLSI build system to organize the ASIC toolflow. We hope that our experience convinces architects that silicon prototyping of RISC-V systems is both feasible and attractive for supporting future research. We present a case study for cost-effective and productive silicon prototyping and describe our experience building BRGTC2 (i.e., Batten Research Group Test Chip 2), a small 1⇥1.25 mm 6.7M-transistor RISC-V system in TSMC 28 nm. BRGTC2 is designed and implemented using PyMTL, a new Python-based hardware modeling framework [5, 6]. Figure 1 shows the chip block diagram including four RISC-V RV32IMAF cores which share a 32kB instruction cache, 32kB data cache, and single-precision floating-point unit along with microarchitectural mechanisms to mitigate the performance impact of resource sharing. The chip also includes a fully synthesizable high-performance PLL written in SystemVerilog and ported from the Celerity SoC [1, 4]. In this paper, we provide an overview of various key aspects of our silicon prototyping experience, including our timeline and costs, open-source software toolchain and ISA, open-source cycle-level modeling, open-source RTL modeling, open-source modular VLSI build system, and synthesizable analog IP. The landscape of connected open-source tools for computer architecture research now extends across the computing stack, making RISC-V silicon prototypes both feasible and attractive as vehicles for future research. Timeline and Costs – Our team of seven graduate students completed the 28 nm SoC in two months. This design Memory Instruction Memory Arbiter L1 Data $ (32KB) LLFU Arbiter Int Mul/Div FPU L1 Instruction $ (32KB) H os t I nt er fa ce Sy nt he si za bl e PL L Arbiter Data Figure 1. Block Diagram of BRGTC2 – We paired the RISC-V ecosystem with productive open-source design tools to build a 1⇥1.25 mm RISC-V system in TSMC 28 nm with seven graduate students in two months. Taped out: May 2018 Silicon: Fall 2018 period encompassed developing simple applications, porting an in-house work-stealing runtime to our RISC-V target, cycle-level design-space exploration of sharing architectures in gem5 [3], RTL development and testing of each component including SRAMs (see Figure 1), composition testing at RTL and gate level, SPICE-level modeling of the synthesizable PLL, IO floorplanning and physical design, post-placeand-route performance tuning, and final tapeout. About one person-month was required for a student with prior ASIC experience to bring up the TSMC 28 nm design flow for the first time, including the process libraries, standard cell libraries, IO cell libraries, Synopsys DC, Cadence Innovus, and Calibre signoff tools, in order to pass DRC/LVS for dummy logic surrounded by staggered IO pads and no SRAM blocks. The entire chip RTL was designed in the final one-month period by seven graduate students using PyMTL for design, test, and composition. Multi-project wafer services have recently begun to support advanced technology nodes (e.g., 28 nm) with very small minimum sizes (e.g., 1⇥1 mm) at very reasonable pricing (e.g., $14K). We chose the Tiny2 program with MOSIS, selecting a 1⇥1.25 mm die size and one hundred parts for about $18K. Other services are also available for university researchers at similar pricing (e.g., Muse Semiconductor [7]). Other costs included packaging (less than $2K for twenty parts), board costs (less than $1K for PCB and assembly), graduate student salaries, physical IP costs, and EDA tool licenses. The open-source RISC-V ecosystem helped us avoid any costs associated with the ISA and also helped avoid long communication delays with third parties, which can take months to resolve and can significantly delay a time-sensitive project. Many small benefits also made a difference (e.g., a very short but descriptive RISC-V ISA spec saving us from reading thousand-page specs, no time and effort required to bring up and modify a software toolchain, open-source VLSI implementations of previously taped out RISC-V SoCs for reference including Rocket [2] and Celerity [1, 4]). Open-Source Software and ISA – The RISC-V software toolchain was tremendously useful as an out-of-the-box and standard solution for compiling applications for our system. In particular, we leveraged recent GCC support with options targeting RV32IMAF, and we were also able to use inline assembly in our in-house work-stealing runtime library to implement hints and to track stats. The RISC-V ISA itself was also a tremendous success. Because the ISA is designed as a small base set of instructions with modular extensions, we were able to apply an incremental design approach by writing RTL to first support the base set (i.e., RV32I), then add multiply/divide support (i.e., RV32IM), then add atomic support (i.e., RV32IMA), and finally add floating-point support (i.e., RV32IMAF). We also leveraged the control and status registers for many custom purposes including tracking stats. Open-Source Cycle-Level Modeling – The gem5 simulator system [3] is a popular platform for simulator-based cycle-level modeling in the computer architecture research community. Multicore support has recently been added for RISC-V [9], providing computer architects a critical tool for cycle-level design-space exploration of complex RISC-V systems. We leveraged RISC-V support on gem5 to explore our sharing architecture shown in Figure 1, which shares caching resources and long-latency functional units. We swept important parameters including the latency to shared resources, the number of each resource to share, the impact of memory coalescing techniques, the size and capacity of caches and buffers, and the impact of various arbitration schemes. Open-Source RTL Modeling – We paired the RISC-V ecosystem with a new Python-based hardware modeling framework, PyMTL [5, 6], to build our RISC-V system. PyMTL leverages the Python programming language to create a highly productive and flexible environment for test, design, and composition in BRGTC2. Testing in PyMTL enables access to full-featured software testing frameworks built for Python (e.g., pytest [8]), providing useful features including automatic test discovery, modular fixtures, and rich customizable plugins. We leveraged PyMTL support for two-state simulation and state initialization to one, zero, and random values. Designing in PyMTL was more accessible than in Verilog for students new to RTL design, avoiding many well-known quirks of the older language while also enabling a familiar style of debugging in Python. Composition in PyMTL enabled powerful multi-level co-simulation of functional-level, cycle-level, and RTL models. For example, to debug an issue with atomics, we swapped in a functional model of the cache to narrow the bug location down to other components. The PyMTL framework generates Verilog for our standard ASIC toolflow. Overall, we found the PyMTL framework to be a tremendous success for designing a RISC-V system from scratch with rigorous testing support. Open-Source ASIC Flow Organization – The availability of high-quality, community-developed reference ASIC flows is a tremendously useful resource for both new and experienced chip designers. We designed our RISC-V silicon prototype (see Figure 2) using a modular VLSI build system1, which we have open-sourced as a reference organization of 1Modular VLSI Build System: https://github.com/cornell-brg/alloy-asic 1.25 mm

This work presents baseband timing circuitry that enables scalable synchronization and aggressive duty-cycling of peer-to-peer IoT nodes for low-power wireless communication. The circuitry is compatible with commercial RF front ends and is insensitive to the phase and frequency offsets of the received signal due to the differential detector. An analog correlator enables low-latency detection of a synchronization packet, or syncword. The detected syncword is used to advance the phase of a nonlinear pulse-coupled oscillator, which drives the network to a synchronized state. The circuits consume 12.46 μW in 0.01 % duty-cycled mode while detecting a 63-bit syncword at 1.25 Mbps with BER = 10 -3 at SNR = 5 dB. Synchronization of three wireless nodes is demonstrated.

Recent work has shown that monolithic integration of voltage regulators will be feasible in the near future, enabling reduced system cost and the potential for fine-grain voltage scaling (FGVS). More specifically, on-chip switched-capacitor regulators appear to offer an attractive trade-off in terms of integration complexity, power density, power efficiency, and response time. In this paper, we use architecture-level modeling to explore a new dynamic voltage/frequency scaling controller called the fine-grain synchronization controller (FG-SYNC+). FG-SYNC+ enables improved performance and energy efficiency at similar average power for multithreaded applications with activity imbalance. We then use circuit-level modeling to explore various approaches to organizing on-chip voltage regulation, including a new approach called reconfigurable power distribution networks (RPDNs). RPDNs allow one regulator to "borrow" energy storage from regulators associated with underutilized cores resulting in improved area/power efficiency and faster response times. We evaluate FG-SYNC+ and RPDN using a vertically integrated research methodology, and our results demonstrate a 10-50% performance and 10-70% energy-efficiency improvement on the majority of the applications studied compared to no FGVS, yet RPDN uses 40% less area compared to a more traditional per-core regulation scheme.