Developing charge-trap flash that can operate reliably at low voltages while supporting quad-level storage requires both controlled charge placement and stable switching behavior throughout repeated cycling. In this study, we introduce a device architecture that combines a thin interfacial layer inside the HfZrOx stack with a charge-trap layer designed to reshape its energy-band profile. Measurements confirm that inserting the interlayer alters the internal polarization response of the dielectric, yielding a broader programmable window, lower program and erase thresholds, and improved step-wise programming characteristics. The modified charge-trap layer further contributes to stable performance by restricting excessive electron injection, resulting in more uniform program and erase transitions even after extended cycling. Collectively, these engineering approaches enable a memory window of 13.6 V, strong incremental programming efficiency, robust disturb immunity, and sustained quad-level storage. A qualitative interpretation based on switching-energy considerations suggests that the interlayer helps maintain a more uniform polarization evolution, while the engineered trap layer reduces interface-driven variation, supporting a dependable platform for future low-voltage quad-level flash technologies

Postdeposition annealing (PDA) with an insulating Al 2 O 3 capping layer is demonstrated as a crystallization strategy for reliable source‐tied covering metal (SCM)‐integrated oxide‐channel ferroelectric field‐effect transistors (FeFETs). Conventional postmetallization annealing (PMA) with TiN promotes high remanent polarization but induces oxygen scavenging, oxygen‐vacancy formation, and interfacial dead layers, which accelerate leakage and cycling degradation. By decoupling HZO crystallization from direct HZO/TiN interaction, the PDA process suppresses interfacial defect generation and stabilizes the ferroelectric/channel stack. Capacitor analysis shows that PDA‐treated HZO exhibits lower leakage current, a thinner interfacial dead layer, and endurance exceeding 10 6 cycles. When integrated into SCM‐integrated FeFETs using an In 2 O 3 channel, the PDA scheme maintains a stable memory window of 12.63 V after 10 3 cycling during ISPP/ISPE operation and preserves an 8.43 V retention window after cycling. The devices further exhibit endurance up to 10 5 cycles, outperforming PMA counterparts that suffer rapid memory‐window collapse. These results establish PDA using an insulating capping layer as an effective route toward reliable, low‐thermal‐budget oxide‐channel FeFETs for high‐density three‐dimensional ferroelectric NAND memory.

Yttrium offers exceptional intrinsic extreme ultraviolet (EUV) transmittance and emissivity for next-generation pellicles. However, its severe oxidation susceptibility limits its practical implementation. In this study, we demonstrate that amorphous carbon (a-C) capping layers effectively preserve metallic Y, whereas plasma-enhanced atomic-layer-deposited SiNx causes catastrophic oxidation. Our standalone a-C/Y/a-C film achieves 86.8

We investigate dipole-first (DF) gate stacks using rare-earth oxides (REOs) to enable scalable multi-Vt options for advanced logic CFET devices. $\text{LaO}_{\mathrm{x}}$ and $\text{GdO}_{\mathrm{x}}$ DF stacks are systematically compared in terms of dipole strength, interface quality, trap charge density, and gate leakage. $\text{LaO}_{\mathrm{x}}$ exhibits strong dipole behavior, resulting in a $\mathrm{V}_{\mathrm{t}}$ reduction of $\sim 155 \text{mV} /$ cycle. $\text{GdO}_{\mathrm{x}}$ shows a moderate dipole effect with a negative Vt shift of $\sim 80 \text{mV} /$ cycle. However, the 1 cycledALD of $\text{GdO}_{\mathrm{x}}$ induced an excessively strong dipole, leading to an abrupt $\mathrm{V}_{\mathrm{t}}$ modulation. Based on this behavior, an imprinted Gd dipole (IGD) gate stack is designed to further modulate the effective dipole strength of a subsequent $\text{LaO}_{\mathrm{x}}$ DF stack. The proposed IGD scheme achieves a fine Vt tunability of $\sim 40 \text{mV} /$ cycle with negligible EOT penalty. In addition, the IGD stack reduces the effective trap density by 92% and suppresses gate leakage current by more than one order of magnitude compared to the conventional $\text{LaO}_{\mathrm{x}}$ DF stack.

For decades, conventional geometric scaling has driven performance improvements in the semiconductor industry. However, the continued reduction in technology nodes has increasingly become decoupled from simple dimensional shrinkage, instead reflecting transitions toward new device architectures, shifts in established process paradigms, and demands for unprecedented process precision. In this context, critical functional layers—such as insulators, metal interconnects, and interfaces—now require atomic- and sub-nanometer-scale control over film profiles and material properties. From this process-centric perspective, the semiconductor industry can be defined as entering an era of Ångström-scale precision. Atomic layer processing (ALP), a unified framework integrating atomic layer deposition, atomic layer etching, and area-selective deposition, has emerged as a key enabling technology for this transition. By leveraging self-limiting surface reactions, ALP enables atomic- and sub-nanometer-scale control over thickness, composition, and selectivity, facilitating void-free film formation in complex three-dimensional architectures, high-precision selective patterning, and atomic-scale engineering of materials and interfaces. Moreover, by bridging deposition, etching, and selectivity within a single chemistry-driven framework, ALP provides a scalable process pathway that extends beyond the limits of conventional geometric and material scaling. Ultimately, ALP represents not merely an incremental process innovation but a paradigm shift toward atomically precise manufacturing, fundamentally redefining how materials, interfaces, and device architectures are realized beyond nanometer-scale control.

We present a ferroelectric nand (FeNAND) cell incorporating an engineered InGaZnO (IGZO) charge trap layer (CTL) within a metal-gate interlayer (G.IL)-oxide semiconductor (OS)-ferroelectric (FE)-channel interlayer (Ch.IL)-semiconductor (MISFIS) gate-stack for highly reliable 3-D integration. Conventional MIFIS-based FeNAND cells suffer from endurance degradation driven by oxygen vacancy (V-O) accumulation and severe memory window (MW) loss during retention caused by charge emission at the G.IL/FE interface. To address these limitations, a 2-nm-thick IGZO CTL is introduced, functioning simultaneously as: 1) an oxygen reservoir that suppresses V-O-induced endurance failure and 2) an energy barrier that mitigates charge loss during retention. Furthermore, in situ N-2 doping is employed to precisely tailor the trap profile, yielding deep-level dominant traps at an N-2 flow rate of 2 sccm. The optimized MISFIS FeNAND cell achieves a wide MW of 9.4 V at an operation voltage below 17 V, stable triple-level cell (TLC) retention over ten years, and robust endurance exceeding 80k program (PGM)/erase (ERS) cycles. These results confirm that the IGZO CTL-based MISFIS architecture overcomes key reliability challenges of conventional FeNAND structures and represents a strong candidate for next-generation high-density 3-D FE memory technologies.

Ru films deposited via atomic layer deposition (ALD) typically exhibit island-like growth on oxide substrates, which degrades their mechanical and electrical properties. The reduction of structural defects in Ru films (including voids within the film bulk and loose bonds at the electrode/dielectric interface) by electrode annealing can increase the capacitance of Ru/ZrO2/Ru capacitors. However, the post-deposition annealing (PDA) of Ru electrodes in such capacitors has not been examined in detail. The capacitance enhancement of Ru/ZrO2/ Ru capacitors was investigated by annealing their top Ru electrodes, which led to film densification. Structural and electrical analyses involving X-ray reflectivity, transmission electron microscopy, and adhesion tests revealed that annealing-induced densification of the Ru film lowered the film resistivity and strengthened interfacial adhesion. Consequently, PDA of the ALD-Ru top electrode resulted in an 11-16% increase in the capacitance of Ru/ZrO2/Ru capacitors compared to those with an as-deposited Ru top electrode.

Extreme ultraviolet (EUV) pellicles must exhibit high optical transmittance, thermal, and mechanical stability to withstand the demands of semiconductor fabrication. ZrSi2 has attracted attention as a pellicle material due to its excellent optical characteristics. The thickness of ZrSi2 films is being reduced to enhance EUV transmittance (EUVT). Since the mechanical strength of nanoscale thin films can be influenced by grain-size effects described by either the Hall–Petch or inverse Hall–Petch relationship, grain-size control becomes critical. In this study, ZrSi2/SiNx free-standing membranes with different ZrSi2 grain sizes were fabricated by sputter deposition followed by annealing at 425–600 °C. Grazing incidence X-ray diffraction analysis confirmed that the ZrSi2 thin films retained their orthorhombic structure up to 600 °C. Scanning transmission electron microscopy showed a gradual increase in grain size with increasing annealing temperature. EUVT remained almost unchanged regardless of the ZrSi2 grain size. In contrast, the ultimate tensile strength increased with grain size up to 64 nm and decreased with further grain growth. These results indicate that although the optical properties of ZrSi2-based EUV pellicles are grain-size independent, their mechanical strength can be optimized through microstructural engineering, consistent with the Hall–Petch relationship.

Polycrystalline silicon (poly-Si) is a promising channel material for three-dimensional (3D) stacked memory architecture owing to its process compatibility and excellent manufacturability. However, its practical application is hindered by intrinsic limitations, such as reduced carrier mobility and elevated off-state current (Ioff), which originate from localized electric fields and trap states at grain boundaries. In this study, the structural characteristics, including the crystallization behavior and grain morphologies, of silicon films deposited by sputtering and low-pressure chemical vapor deposition (LPCVD) were comparatively investigated. Raman spectroscopy and cross-sectional transmission electron microscopy (TEM) results confirmed that LPCVD poly-Si annealed at 800 °C exhibits over 95% crystallinity and a columnar-like grain structure. Based on this structural superiority, transistor-level electrical characterizations were exclusively conducted on LPCVD-based devices. The results show that the Ioff of annealed poly-Si depends on the channel width, with normalized Ioff values being lower when the channel is narrower than the average grain size. Further, a larger grain size with a columnar structure in poly-Si can maintain acceptable Ioff levels in 3D stacked memory devices incorporating narrow channel widths.

A conformal SiNx coating on carbon nanotubes (CNTs) was achieved by combining transient UV-ozone surface functionalization with a two-step atomic layer deposition (ALD) process. UV-ozone treatment gradually increased the defect density of CNTs, with the ID/IG ratio increasing from 0.05 for pristine CNTs to 0.25 after 7 min of exposure, while the overall fibrous CNT network remained intact. However, prolonged UV-ozone exposure beyond 10 min led to a sharp increase in the ID/IG ratio to 0.46, accompanied by structural degradation of the CNT membrane. Hydroxyl (-OH), epoxy (C-O-C), and carbonyl (C=O) groups were introduced by UV-ozone treatment and were partially removed during subsequent high-temperature processing. Accordingly, direct high-temperature ALD resulted in incomplete SiNx coverage of the CNTs, suggesting insufficient nucleation. A two-step ALD process, consisting of several cycles of low-temperature nucleation at 100 °C followed by high-temperature growth at 700 °C, enabled more conformal deposition of SiNx on CNTs. In addition, both annealing and ALD reduced the defect level toward that of pristine CNTs, supporting the transient nature of UV-ozone-induced functionalization.

Thermal atomic layer deposition of silicon nitride (SiNx) as a conformal protective coating was investigated to enhance the hydrogen-plasma resistance of carbon nanotube (CNT) pellicles for extreme ultraviolet (EUV) lithography. SiNx films were deposited on Si wafers and free-standing CNT membranes in a tube-type furnace using Si2Cl6 and NH3 precursors, and the growth behavior was systematically examined over 500-800 degrees C. An effective ALD window was identified at 650-700 degrees C, yielding a growth per cycle of similar to 1.9 & Aring;/cycle. The deposited films on both Si wafers and CNT membranes exhibited Si-N-dominant bonding with no significant compositional difference between the substrates, together with low oxygen incorporation and negligible chlorine residues. After ozone pretreatment, continuous and conformal SiNx coatings were formed over the CNT network. The optical impact of the coating was evaluated at 13.5 nm; SiNx-coated CNT pellicles exhibited 95.2 % EUV transmittance, corresponding to a 2.5 percentage-point reduction compared with bare CNT pellicles. Hydrogen plasma exposure tests showed severe degradation of uncoated CNT pellicles, whereas SiNx-coated CNTs retained their morphology. These results demonstrate that thermal deposition of SiNx is an effective protective coating strategy for improving the durability of CNT pellicles in EUV lithography environments.

In this work, we demonstrate asymmetric doublegate (ADG) FeFETs utilizing sub-3.5 nm ultrathin HZO, achieving a wide memory window (MW) of 1.3 V at a logiccompatible operating voltage of 1.8 V. While aggressive ferroelectric thickness scaling is essential for reducing operating voltage, it typically suffers from severe polarization degradation and MW loss due to phase instability. We address this challenge by introducing a gate-coupling-ratio engineering approach within an ALD-based 3D-compatible process. The proposed ADG-FeFET exhibits a $3.4 \times$ larger MW compared to conventional single-gate FeFETs and demonstrates superior reliability. Furthermore, the potential for analog compute-inmemory (CIM) is validated through stable multilevel operation with high linearity and system-level simulations. These results provide a practical pathway toward low-voltage, high-density FeFET technologies and next-generation analog CIM systems.

Nanometer-thick membranes, including extreme ultraviolet (EUV) pellicles, require temporary protection during wet-based Si bulk etching. This sacrificial layer must shield the target membrane from the Si etchant and be removable after membrane fabrication. Here, sputtered Cu is introduced as a sacrificial protection layer for Mo₂C-based membrane fabrication. Cu exhibited strong resistance to a 30 wt

A vapor-phase dry development process utilizing the beta-diketone compound hexafluoroacetylacetone (hfacH) was applied to a nanoscale zinc-based metal-organic photoresist (ZnOR) with a vertically aligned molecular wire architecture. X-ray photoelectron spectroscopy (XPS) confirmed that exposure-induced Zn-O-Zn and Zn-S-Zn coordination networks remained intact during vapor-phase dry development, while unexposed regions underwent rapid Zn removal via beta-diketone chelation. The development is governed by a surface-reaction-limited mechanism that suppresses developer penetration and resists swelling, in contrast to conventional wet development. Although the vapor-phase process exhibits a development contrast (gamma = 1.18) lower than that of wet development (gamma = 1.77), it achieves superior dimensional control in terms of pattern-to-pattern critical dimension (CD) variability at the nanoscale. Under identical exposure conditions, vapor-phase dry development enabled stable line-and-space patterning down to a 14 nm critical dimension with a development selectivity of 5.8. Pattern-to-pattern CD uniformity was significantly improved, yielding 3 sigma = 2.07 nm for 50 nm half-pitch square arrays, corresponding to an approximately 35% reduction in CD variation compared to conventional wet development. These results suggest that CD uniformity of nanoscale features is governed not solely by development contrast but by the stability of the reaction front during development, establishing beta-diketone-mediated vapor-phase dry development as a robust strategy for reliable dimensional control in terms of pattern-to-pattern CD variability in Zn-based metal-organic EUV photoresists.

Extreme ultraviolet (EUV) ptychography is a promising actinic mask metrology technique capable of subwavelength and aberration-free imaging. However, its performance is limited by EUV absorption and insufficient acquisition of high-frequency (HF) diffraction signals. This study demonstrates resolution enhancement via probe refinement using a small-etendue high harmonic generation-EUV source and an illumination aperture. The source was upgraded with a narrower-bandwidth infrared driving laser, improving coherence and boosting EUV power by over 80x. Under an optical system with a 0.155 numerical aperture and 6 degrees oblique mask illumination, Fourier transform-based simulations and experimentally obtained diffraction patterns of a Siemens star revealed a 2.69x improvement in the signal-to-noise ratio of HF diffraction signals and a 120% extension in maximum detected spatial frequency. Eventually, these enhancements enabled a reconstructed image resolution corresponding to 11.5 nm at the wafer plane. The reduced Fourier error further validated the improved phase retrieval, confirming EUV ptychography as a reliable and high-resolution actinic mask metrology tool for next-generation EUV masks.

Abstract Hafnia-based ferroelectric tunnel junctions (FTJs) are promising candidates for high-density nonvolatile memory due to their compatibility with CMOS technology. However, their adoption is hindered by low tunneling electroresistance (TER), poor endurance, and sneak currents in high-density array architectures. Here, we report a self-rectifying metal–interlayer–ferroelectric–metal (MIFM) FTJ through simultaneous electrode work-function engineering and the introduction of oxide interlayers to induce asymmetric barrier modulation and serve as oxygen reservoirs for the ferroelectric layer. By systematically comparing InO, IZO, and ZnO interlayers, we confirm ZnO as the optimal interlayer to maximize the barrier asymmetry while suppressing interface defects due to its superior oxygen reservoir (OR) capability, yielding a giant TER ratio of 34,000 and a rectifying ratio (RR) of 1150. Interface analysis reveals a thinner interfacial dead layer, a larger domain size, a 15% lower trap density, and reduced sub-oxide formation in ZnO compared to InO and IZO FTJs, which collectively contribute to superior endurance up to 108 cycles, stable 10 year retention, and low device-to-device variation. Moreover, read margin simulation demonstrates that ZnO-based FTJs support larger crossbar array sizes than InO- and IZO-based FTJs by more effectively suppressing sneak-path currents, highlighting oxide-interlayer engineering as a promising design strategy for improving the reliability and scalability of hafnia-based ferroelectric memory.

Extreme ultraviolet lithography (EUVL, λ = 13.5 nm) is critical for sub-1 nm technology nodes but remains constrained by inherent trade-offs among resolution, line-edge roughness (LER), and sensitivity. Stochastic effects originating from photon shot noise, low-energy secondary electron blur, and the random distribution of resist components further limit its advancement toward high numerical-aperture (NA, NA = 0.55) and hyper-NA (NA ≥0.75) EUVL. While the optimization of spin-on chemically amplified resists (CARs) continues, metal-oxide resists (MORs) have emerged as strong candidates for next-generation EUVL by incorporating metals with high EUV absorption coefficients, which enhances both resist sensitivity and etch resistance during pattern transfer. Besides spin-coating, recent advances in vapour-phase techniques, such as vapour-phase infiltration (VPI), chemical vapour deposition (CVD), and molecular atomic layer deposition (MALD), offer promising pathways to achieve new resist platforms, such as dry resists, that satisfy the stringent thickness and uniformity requirements of next-generation EUVL. These methods enable the direct incorporation of metal species into existing resist matrices or the formation of hybrid inorganic-organic resist platforms, thereby improving film uniformity, etch durability, and pattern fidelity while mitigating stochastic defects. This review highlights the latest advancements in vapour-phase-synthesized EUV resists, emphasizing material design, lithographic performance, and the underlying exposure mechanisms. Although still emerging, vapour-phase strategies are paving the way for an all-dry integration framework that could improve EUV patterning workflows and meet the demands of future technology nodes.