Next generation of quantum computers calls for reduced dc power dissipation of the cryogenic low-noise amplifier (LNA) applied in reading out the superconducting qubits. This article reports on processing and evaluation of a 100-nm gate length indium phosphide high electron mobility transistor (InP HEMT) technology used in the design of such LNAs. InP HEMTs with size of 4 & times; 50 & micro;m were measured on-wafer by DC and S-parameter characterization. Device noise performance was indirectly evaluated by measuring and modeling the gain and noise of a three-stage hybrid 4-8 GHz cryogenic LNA equipped with the InP HEMTs. When operating the LNA at a DC power of 2.1 mW, the InP HEMT LNA average noise temperature was 1.4 K with an average gain of 41.6 dB. The minimum noise temperature of the InP HEMT was estimated to be 1.1 K at 6 GHz. The performance achieved for the InP HEMT LNA is comparable to the LNAs currently used in quantum computing while requiring only 27% of the DC power consumption. Small-signal modeling of the InP HEMT suggested that this was due to a low output conductance associated with a large gate-recess length used in device fabrication.

Current methods for transferring III-V technology onto silicon are based on wafer bonding techniques. Here we explore fabrication applicability of traditional InP-based High Electron Mobility Transistors (InP HEMTs) on InP-on-Si (InPoSi) wafers developed by Smart Cut, a method for transferring InP onto Si that reduces cost and fabrication complexity. We fabricated 100-nm gate length InP HEMTs, including test structures and Hall bars on both InPoSi and InP wafers. Transfer Length Method (TLM) measurements for InPoSi and InP bulk wafers showed comparable contact and sheet resistances. These preliminary results show that InP HEMTs can be fabricated on InPoSi.

Assessing short channel effects (SCEs) is crucial in the high-frequency optimization of downscaled field-effect transistors (FETs) such as GaN high electron mobility transistors (HEMTs). Drain-induced barrier lowering (DIBL) is commonly used for quantifying the ability of the gate to modulate the drain-source current at high drain voltages. DIBL is traditionally extracted from the relative shift of the threshold voltage at different drain-source voltages. In this article, we propose a new method based on a drain current injection technique (DCIT) to assess DIBL. This method facilitates a direct measure of the threshold voltage over a wide range of drain-source voltages in a single measurement. The method is demonstrated and compared to the conventional method using AlGaN/GaN and InAlGaN HEMTs with a Fe-doped buffer and a C-doped AlGaN back-barrier, respectively. Furthermore, the impact of different gate lengths and GaN channel layer thicknesses is presented. The measurements are analyzed and discussed with supporting technology computer-aided design (TCAD) simulations. The proposed method facilitates a more general and detailed measurement of the DIBL for HEMTs.

The InP high-electron-mobility transistor (HEMT) is employed in cryogenic low-noise amplifiers (LNAs) for the readout of faint microwave signals in quantum computing. The performance of such LNAs is ultimately limited by the properties of the active In(x)Ga(1-x)A(s )channel in the InP HEMT. In this study, we have investigated the noise performance of 100-nm gate-length InP HEMTs used in cryogenic LNAs for amplification of qubits. The channel indium content in the InP HEMTs was 53, 60 and 70%. Hall measurements of the epitaxial materials and dc characterization of the InP HEMTs confirmed the superior transport properties of the channel structures. An indirect method involving an LNA and small-signal noise modeling was used for extracting the channel noise with high accuracy. Under noise-optimized bias, we observed that the 60% indium channel InP HEMT exhibited the lowest drain noise temperature. The difference in LNA noise temperature among InP HEMTs became more pronounced with decreasing drain voltage and current. An average noise temperature and average gain of 3.3 K and 21 dB, respectively, for a 4-8 GHz three-stage hybrid cryogenic LNA using 60% indium channel InP HEMTs was measured at a dc power consumption of 108 mu W . To the best of the authors' knowledge, this is a new state-of-the-art for a C-band LNA operating below 1 mW. The higher drain noise temperature observed for 53 and 70% indium channels InP HEMTs can be attributed to a combination of thermal noise in the channel and real-space transfer of electrons from the channel to the barrier. This report gives experimental evidence of an optimum channel indium content in the InP HEMT used in LNAs for qubit amplification.

4 – 8 GHz low-noise amplifiers (LNAs) based on InP high electron mobility transistors (InP HEMTs) with different spacer thickness in the InAlAs-InGaAs heterostructure were fabricated and characterized at 5 K. A variation in the lowest average noise temperature of the LNA was observed with spacer thickness. We here report that the subthreshold swing (SS) at 5 K for the HEMT exhibited similar dependence with spacer thickness as the lowest average noise temperature of the LNA. This suggests that low-temperature characterization of SS for the HEMT can be used as a rapid assessment of anticipated noise performance in the cryogenic HEMT LNA.

InP high electron mobility transistors (InP HEMTs) with different spacer thickness 1 to 7 nm in the InAlAs-InGaAs heterostructure have been fabricated and characterized at 5 K with respect to electrical dc and rf properties. The InP HEMT noise performance was extracted from gain and noise measurements of a hybrid low-noise amplifier (LNA) at 5 K equipped with discrete transistors. When biased for optimal noise operation, the LNA using 5 nm spacer thickness InP HEMTs achieved the lowest average noise temperature of 1.4 K at 4–8 GHz. The InP HEMT channel noise was estimated from the drain noise temperature which confirmed the minimum in noise temperature for the 5 nm spacer thickness InP HEMT. It is suggested that the spacer thickness acts to control the degree of real-space transfer of electrons from the channel to the barrier responsible for the observed noise variation in the cryogenic InP HEMTs.

Poststress dc characteristics of AlGaN/GaN HEMTs can be used to study the effect of high-power stress on the noise figure (NF) and gain of low-noise amplifiers (LNAs) subjected to large input overdrives. This enables a shift from circuit- to transistor-level measurements to investigate the impact of variations in HEMT design parameters on the robustness (including both recovery time and survivability) by mimicking LNA operation. Using this method, a tradeoff between survivability and recovery time is demonstrated for different AlGaN/GaN interface profiles (sharp interface, standard interface, and AlN interlayer). Furthermore, the impact of different surface passivation schemes (Si-rich, Si-poor, and bilayer SiNx) on robustness is investigated. The bilayer passivation, which features low leakage current and small gain compression under overdrive stress, exhibits relatively weak survivability. The mechanisms influencing the robustness are analyzed based on transistor physics. The short recovery time is mainly due to impeding the injection of hot electrons into surface traps and high reverse current, whereas the survivability is dependent on the local or global peak electrical fields around the gate under high power stress.

This study analyzes the mechanism behind signal demodulation in GaN high-electron-mobility transistors, finding the relationship between gate bias voltage and relative amplitude of the output voltage. The optimal gate bias for maximum responsivity has been analytically found. The responsivity of the GaN demodulator at different biases has been characterized using an on–off keying signal with a 90 GHz carrier. Furthermore, from the measured eye diagram it is observed that the GaN demodulator can demodulate a signal with a maximum data rate up to a 1.28 gigabits per second. This study presents a promising method for integrating a GaN demodulator into a single-chip GaN transceiver.

GaN HEMTs have a great potential to be well suited for the forthcoming 5G communication infrastructures and other millimeter wave applications, where high-power and high-efficient devices are required. For GaN HEMT heterostructures used in high-frequency applications (> 8 GHz), semi-insulating (SI) SiC is the best choice of substrates, owning to its high thermal conductivity and high resistivity, and the maturity in large-wafer mass production (up to 150 mm). Nevertheless, the typical thickness of a GaN layer grown on SiC substrates has to be at least 1.5~2.0 µm to obtain a structural quality manufacturable for device fabrication, due to the large in-plane lattice mismatch with GaN (3.4%). As a result, the thick GaN layer must be doped with acceptor-like impurities like carbon or iron [1] during the epitaxial growth to increase the resistivity, preventing a parallel conduction in the device. However, these impurities introduce deep traps, which capture electrons during the RF operation, rendering a depletion of the channel electrons thus reducing the device current/power density. We report the realization of a revolutionary heterostructure of III-nitride materials grown on SiC substrates by a unique MOCVD method. Our success in the material growth enabled a new design of HEMT heterostructures requiring no intentional Fe- or C-doping. Excellent DC and RF performances of the highly-scaled GaN-based high electron mobility transistors (HEMTs) using the proposed new heterostructures are demonstrated. The new HEMT heterostructures also open up new opportunities in material growth schemes to further reduce the charge trapping effects that have been prevailing in the field over that last two decades. Consequently, a high RF output power of ~4 W/mm was obtained at a fundamental frequency of 30 GHz in the HEMT devices with a gate length (Lg) of 0.1 µm, biased at VDS= 30 volt. We also found that the thermal resistance of the new HEMT devices exhibits a substantially lower thermal resistance (RTH) of 4.1 oC mm/W, as compared with that of the conventional ones, which is typically around 9~10 oC mm/W [2] The details of the new heterostructures and device characteristics will be presented. Our breakthrough in the material growth has brought the GaN HEMT technology to a new height and will serve as a new route for further improvement. IV.References [1] J.-T. Chen et al, Appl. Phys. Lett. 102, 193506 (2013). Impact of residual carbon on two-dimensional electron gas properties in AlGaN/GaN heterostructure. [2] J. Joh et al, IEEE Trans. Elec. Dev. 56, 2896 (2009) Measurement of Channel Temperature in GaN High-Electron Mobility Transistors. Figure 1

We report enhanced gate stack stability in GaN metal insulator semiconductor high electron mobility transistors (MISHEMTs) by using a bilayer SiNx as the gate dielectric. To obtain the bilayer gate dielectric scheme, a thin Si-rich SiNx interlayer was deposited before a high-resistivity SiNx layer by low pressure chemical vapor deposition. The Si-rich SiNx can effectively suppress the trapping phenomenon at the interface of the dielectric/AlGaN barrier. The upper high-resistivity SiNx layer can greatly block the gate leakage current to enable a large gate swing. Compared with the MISHEMTs using a single Si-rich or high-resistivity SiNx layer, the MISHEMTs with a bilayer gate dielectric take the advantages of both, realizing a gate stack with a stable threshold voltage and low leakage current. These results thus present great potential for developing high-performance GaN MISHEMTs using the bilayer SiNx gate dielectric scheme for highly efficient power applications.

This paper presents a study of the lateral heat propagation in an aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure grown on a silicon carbide substrate. The study is enabled by the design of a temperature sensor that utilizes the temperature-dependent I-V characteristic of a semiconductor resistor, making it suitable for integration in GaN monolithic microwave integrated circuit technologies. Using the sensor, we are able to characterize the thermal transient response and extract lateral thermal time constants from the measurements. Time constants in the range from 25 mu s to 1.2 ms are identified. Furthermore, the heat propagation properties are characterized for heat source-to-sensor distances of 86-484 mu m, resulting in delay times from 3.5 to 111 mu s. It is shown that both the time constants and propagation delay increase with temperature. An empirical model of the sensor current versus temperature and voltage is proposed and used to predict the junction temperature of the sensor. The study provides knowledge for heat management design and proposes an integrated temperature measurement solution for future highly integrated GaN applications.

The combination of compact size and low efficiency at mm-waves has turned heat dissipation into a fundamental constraint for design of multi-antenna radios. This paper describes methods for analysis of thermal effects at both at the circuit, system and component level. The first part describes how thermal analysis can be combined with advanced RF modeling techniques to predict self-heating and thermal coupling in multi-antenna transmitter systems. Experimental methods are then used to determine thermal coupling effects occurring at chip level. Various experimental and theoretical results, using MIMO amplifiers and GaN HEMTs, are used to demonstrate the methods in realistic application scenarios.

This paper investigates AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated on epistructures with carbon (C)-doped buffers. Metalorganic chemical vapor deposition is used to grow two C-doped structures with different doping profiles, using growth parameters to change the C incorporation. The C concentration is low enough to result in n-type GaN. Reference devices are also fabricated on a structure using iron (Fe) as dopant, to exclude any process related variations and provide a relevant benchmark. All devices exhibit similar dc performance. However, pulsed I-V measurements show extensive dispersion in the C-doped devices, with values of dynamicRON 3-4 times larger than in the dc case. Due to the extensive trapping, the devices with C-dopedbuffers can only supply about half the outputpower of the Fe-doped sample, 2.5 W/mm compared to 4.8 W/mm at 10 GHz. In drain current transient measurements, the trap filling time is varied, finding large prevalence of trapping at dislocations for the C-doped samples. Clusters of C around the dislocations are suggested to be the main cause for the increased dispersion.

We demonstrate that 3.5% in-plane lattice mismatch between GaN (0001) epitaxial layers and SiC (0001) substrates can be accommodated without triggering extended defects over large areas using a grain-boundary-free AlN nucleation layer (NL). Defect formation in the initial epitaxial growth phase is thus significantly alleviated, confirmed by various characterization techniques. As a result, a high-quality 0.2-μm thin GaN layer can be grown on the AlN NL and directly serve as a channel layer in power devices, like high electron mobility transistors (HEMTs). The channel electrons exhibit a state-of-the-art mobility of >2000 cm2/V-s, in the AlGaN/GaN heterostructures without a conventional thick C- or Fe-doped buffer layer. The highly scaled transistor processed on the heterostructure with a nearly perfect GaN–SiC interface shows excellent DC and microwave performances. A peak RF power density of 5.8 W/mm was obtained at VDSQ = 40 V and a fundamental frequency of 30 GHz. Moreover, an unpassivated 0.2-μm GaN/AlN/SiC stack shows lateral and vertical breakdowns at 1.5 kV. Perfecting the GaN–SiC interface enables a GaN–SiC hybrid material that combines the high-electron-velocity thin GaN with the high-breakdown bulk SiC, which promises further advances in a wide spectrum of high-frequency and power electronics.

Three types of SiNx passivation for microwave AlGaN/GaN HEMTs were deposited with low-pressure chemical vapor deposition under different deposition conditions, resulting in different silicon contents. The performance of the HEMTs is comprehensively investigated and compared. Both small- and large-signal analyses, such as generation–recombination (G–R) trap analysis, low-frequency noise characterization, and load–pull measurement, are indispensable to evaluate the effectiveness of a surface passivation. A Si-rich SiNx passivation shows excess G–R centers, whereas a Si-poor SiNx passivation exhibits significant current slump (30%). A bilayer SiNx passivation successfully shows not only a small current slump (~9.7%) but also a suppressed G–R trapping/detrapping process. Moreover, the bilayer passivation demonstrates almost 2 orders of magnitude lower gate current noise spectra compared with the single-layer Si-rich SiNx passivation. The capacitance-voltage measurements reveal that the Si-rich SiNx layer removes the deep-level traps at the AlGaN/SiNx interface. Considering both small- and large-signal operations, it is concluded that the bilayer SiNx passivation is a suitable and versatile candidate for microwave GaN devices.

Deeply recessed ohmic contacts for GaN-based high electron mobility transistors (HEMTs) are demonstrated. It is shown that low-resistance ohmic contacts can be achieved with recessing beyond the AlGaN Schottky barrier where the ohmic contacts are formed on the sidewall of the recess. This makes the process versatile and relatively insensitive to the exact recess depth. The ohmic contact is based on a gold-free metallization scheme consisting of a Ta/Al/Ta metal stack requiring a low-temperature annealing. Important parameters for this type of ohmic contact process include the metal coverage, slope of the etched sidewall, bottom Ta-layer thickness, as well as annealing temperature and duration. The optimized contact resistance is as low as 0.24 Ω mm after annealing at 575 °C. Moreover, this sidewall contact approach was successfully implemented on different epitaxial heterostructures with different AlGaN barrier thickness as well as with and without AlN exclusion layer. All the samples exhibited excellent contact resistances in a wide range of recess depths. The Ta-based, sidewall ohmic contact process is a promising method for forming an ohmic contact on a wide range of GaN HEMT epitaxial designs.

Three transistors with different AlGaN/GaN interface designs (sharp interface, standard interface, and an extra AlN interlayer) were studied in-depth under conditions mimicking low-noise amplifiers (LNAs) operation. A new measurement setup, analog to LNAs operation condition, is established to measure recovery time on device level. For the first time, a direct relationship between the recovery time and the design of AlGaN/GaN interface is revealed in devices with Carbon doping buffer in this letter. An extremely low-recovery time is demonstrated in the transistor with an AlN interlayer. Both transistors without an AlN interlayer exhibit severe gain and drain current degradation after pulsed input stress. The transistor with a sharp interface shows a recovery time around 10 ms, whereas the transistorwith a standard interface shows even much longer recovery time. These results imply that AlN interlayer, which can effectively block the injection of hot electrons to AlGaN bulk or surface traps, is highly preferred in systems where LNAs need to function promptly after an input overdrive.