Voltage conversion between low-voltage core logic and high-voltage peripheral devices is critical for three-dimensional integrated circuits (3D-ICs). Amorphous indium-gallium-zinc oxide (a-IGZO) high-voltage thin-film transistors (HVTFTs) are promising but are limited by self-heating effect (SHE) and bias temperature instability (BTI) under high-voltage/current operation. This work presents a Corbino offset HVTFT (COHVTFT) featuring an edgeless concentric geometry. This geometry suppresses electric-field crowding and mitigates SHE, thus enhancing robustness for high-voltage switching. The fabricated devices operate stably at 12 V, with off-state and on-state breakdown voltages of 83 V and 47 V, and achieve a switching frequency of 2.24 MHz, suitable for low-frequency high-voltage power applications. A 1T1R inverter confirms the voltage conversion function. Reliability tests show a threshold voltage shift (ΔVth) of 0.12 V under Vgs=3 V and ISTR=5 mA at 55 °C. Furthermore, a folding Dickson multi-ratio switched-capacitor voltage regulator implemented with COHVTFTs provides layer-specific supply voltages for low-power on-chip loads in 3D-ICs. Simulation results demonstrate that the regulator achieves conversion efficiencies exceeding 95% for 4:1, 3:1, and 2:1 step-down voltage conversion ratios across a 0–12 V input range.
Computing-in-memory (CiM) has emerged as a promising solution to overcome the memory wall in data-intensive applications. However, conventional oxide semiconductor-based memory devices suffer from limited retention and insufficient multibit capability, restricting their practical deployment. In this work, a hybrid 1T–1MFMIS ferroelectric field-effect transistor (FeFET) memory cell, consisting of a dedicated write transistor (Wtr) and a physically separated MFMIS FeFET read transistor (Rtr), is proposed for nonvolatile computing-in-memory applications. By leveraging the synergistic interaction between ferroelectric (FE) polarization and charge trapping (CT) effects, the device achieves a large memory window of 2.3 V and a high on/off ratio of $\sim 10^{6}$ . The MFMIS Rtr exhibits endurance up to $10^{8}$ cycles at room temperature. Its two-state retention was measured to 1000 s and extrapolated to 10 years at room temperature. The complete 1T–1MFMIS cell demonstrates 3 bit/cell (8 levels), with retention measured to 2000 s at room temperature. System-level simulation using DNN+NeuroSim V1.4 yields an energy efficiency of 75.63 TOPS/W under the specified simulation conditions. These results highlight the strong potential of the proposed 1T–1MFMIS FeFET for high-density and energy-efficient CiM applications.
This work investigates the impact of channel length (L) on the electrical performance of 4H-Silicon Carbide (4H-SiC) CMOS transistors at room temperature, where L is varying from 20 μm down to 1 μm. The channel width (W) is 20 μm for PMOS transistors and 10 μm for NMOS transistors, which is constant throughout the study. Key electrical parameters in this work include threshold voltage (Vth), transconductance (gm), output conductance (gds), Normalized ON-resistance (RON), and intrinsic voltage gain (Av) under load and no-load conditions. From measurements, it is observed that for transistors with longer channels (LP > 5 μm for pMOSFETs (PMOS) and L > 3 μm for nMOSFETs (NMOS)), Vth remains almost constant at –8.6 V for PMOS and 6.4 V for NMOS, respectively. On the other hand, short channel transistors (L ≤ 5 μm for PMOS and L ≤ 3 μm for NMOS) show a Vth variation of around 2.8 V and 1.9 V, respectively. The normalized RON increases linearly with channel length for both the PMOS (from 512 kΩ·μm to 2700 kΩ·μm) and NMOS (from 49 kΩ·μm to 1200 kΩ·μm) transistors. gm and gds are decreasing with increasing L for PMOS and NMOS, following inverse and inverse-square relationships, respectively. Av,NL increases with L from 1.2 V/V to 315.4 V/V for PMOS and 5.5 V/V to 500.0 V/V for NMOS under no-load condition. These no-load parameters represent intrinsic technology parameters. Further, Av is validated using a CS amplifier with current source as a load, where the output voltage is measured using an oscilloscope (load i.e., RL). This gain is in agreement with the extracted values from the IV characteristics under the same loading conditions. This work provides crucial information about the important electrical parameters required for circuit design, mainly to implement circuits and systems using the emerging 4H-SiC CMOS technology.
The performance and sensitivity analysis of the dielectrically modulated gate-overlap source pocket tunnel FET (GO-SP-TFET) biosensor is presented and compared to that of the source pocket tunnel FET (SP-TFET) biosensor via TCAD simulation studies. In the proposed structure, the advantages of gate-overlap together with those of source-pocket engineering provide better electrostatic control and stronger BTBT at the source-channel junction interface, resulting in the improvement in sensing performance. The proposed biosensor utilizes the modulation of dielectrics in nano cavities for performing biosensing operations. The effects of important parameters like the dielectric constant of biomolecules, cavity size, oxide thickness, and steric hindrance are studied systematically. It is observed that the proposed GO-SP-TFET biosensor provides excellent electrical performance in terms of higher ON current, lower subthreshold swing, and electrostatic integrity than the conventional SP-TFET design. With high permittivity biomolecules (K = 12), the sensitivity of the proposed GO-SP-TFET biosensor reaches up to 1.339, exhibiting better current modulation, selectivity, and LOD. These performance improvements are primarily because of the better field intensity and tunneling barrier reduction due to gate-overlap structure.
This paper presents a complementary metal–oxide–semiconductor (CMOS) microelectrode array (MEA) platform featuring narrow-line aluminum mesh electrodes with top-side and back-side post-processing for combined optical imaging and extracellular electrophysiological recording. The device is fabricated using a 200 nm silicon-on-insulator (SOI) CMOS process and consists of a 20 × 40 array of aluminum mesh electrodes, each addressed by an integrated nMOS transistor for matrix-style sensing. To enable optical observation, back-side openings down to the buried oxide (BOX) layer beneath the electrodes are fabricated, providing partial optical transmission. A transparent conductive layer of indium tin oxide (ITO) is selectively deposited on the aluminum mesh electrode surfaces to allow electrical sensing, while maintaining optical semi-transparency and biocompatibility. Electrical characterization demonstrates that the ITO modification preserves transistor functionality through the CMOS addressing circuitry. Cardiomyocytes from neonatal mice are cultured directly on the CMOS MEA with ITO-modified electrodes, exhibiting good adhesion and spontaneous contractile activity. Extracellular electrical signals generated by the cultured cardiomyocytes are successfully recorded using a commercial acquisition system. An additional CMOS MEA platform is post-processed by incorporating vertical through-holes within the mesh of each electrode and back-side openings to enable future integration of biochemical sensing or microfluidic access. By combining semi-transparent electrodes, integrated transistors, and vertical through-hole structures, this work establishes a versatile SOI-CMOS MEA platform for simultaneous optical imaging and electrical recording, with potential for future multimodal sensing applications.
