Tantalum pentoxide (Ta2O5) films were formed by oxidizing thin tantalum (Ta) films on bare and NO-nitrided silicon substrates. The 43-400 Å thick Ta films were deposited using physical vapor deposition (PVD) and oxidized using O2 for 2-60 min at 550-800 C in a furnace or single wafer tool. Uniform and stoichiometric Ta2O5 films were successfully produced as determined from XRD, AES depth profiling, XTEM, and ellipsometric analysis. The nitridation pretreatment was found to minimize the interfacial Ta-Si reactions which occur during the oxidation. Well-behaved CV and IV curves were obtained from mercury probe measurements. No CV hysteresis was observed. An equivalent oxide thickness of 38 Å and a leakage current of 7×10−9 A/cm2 at +1V were obtained for a 120 Å thick Ta2O5 film on a 15 Å interfacial SiO2 layer.

Silicide materials (NiSi, COSi2, TiSi2, etc) are used to form low-resistance contacts between the back-end (W plugs and Cu interconnects) and front-end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from COSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active (monocrystalline) and gate (polycrystalline) lines. Like its predecessors TiSi2 and COSi2, NiSi is a mid-gap silicide, i.e., the Fermi level of the NiSi metal is pinned half-way between the conduction and valence band edges in silicon. This leads to a Schottky barrier between the silicide and silicon source-drain regions, which creates undesirable parasitic resistances. For future CMOS generations, band-edge silicides, such as PtSi for contacts to p-type or rare earth silicides for contacts to n-type Si will be needed. This paper reviews metrology and characterization techniques for NiSi process control for development and manufacturing, with special emphasis on x-ray reflectance and x-ray fluorescence. We also report measurement methods useful for development of a PtSi PMOS module.

This paper compares the performance and inter-die variability of doped and undoped channel multiple-gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrow-width planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar devices, conversions to undoped channel FinFETs is necessary. Furthermore, good short-channel control has to be maintained since undoped channel devices exhibit increase sensitivity to Tbody relative to doped channel FinFETs due to enhanced fully-depleted channel electrostatics

Using a novel fluorinated TaxCy/high-k gate stack, we show breakthrough device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far

The ability to carefully engineer ultra‐shallow junctions close to the gate is critical for high performance advanced CMOS devices. Electron holography (EH) has been proposed and investigated as one of the promising techniques for mapping dopant profiles at a nanometer scale in two‐dimension (2D). We have developed a low‐damage and reproducible sample preparation technique (based on polishing) to prepare samples suitable for EH imaging. Accurate measurements of electro‐static potentials across ultra‐shallow junctions (both N and P type) by EH have been obtained. Potential profiles derived from ultra‐shallow junctions (in the range of 10–30 nm) closely match simulated profiles calculated from secondary ion mass spectroscopy (SIMS) doping profiles of the same junctions. This sets a good baseline for extending the application of electron holography to the quantitative mapping of 2D dopant profiles at close to nanometer spatial resolution.

Extract HTML view is not available for this content. However, as you have access to this content, a full PDF is available via the ‘Save PDF’ action button. Extended abstract of a paper presented at Microscopy and Microanalysis 2005 in Honolulu, Hawaii, USA, July 31--August 4, 2005

We report for the first time performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO2 gate dielectric and TaSiN gate material. The transistors feature 100-150 Angstrom silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing,for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high K dielectric and metal gate on the performance of ultrathin film FD SOI devices.

A vertical double gate MOSFET structure with a new gate stack architecture has been demonstrated. The gate stack consists of two isolated polysilicon regions that are doped N+ and P+ with a metal/polysilicon strap connecting the doped regions. The device has an undoped channel yet performs as an enhancement mode MOSFET due to the asymetric doping of the gate regions on either side of the channel. The advantages of this structure include: 1) reduction of the Vt variations caused by dopant fluctuation in the channel region; 2) enhanced mobility due to an undoped channel region; 3) flexibility to adjust Vt across a wide range from depletion mode to very high Vt depending on the application; 4) lower interconnect resistance due to the use of metal/polysilicon gate components; 5) better manufacturability due to easier patterning of gate over spacer. The devices are enhancement mode with Vt /spl sim/=(0.1-0.3V) at 100 nm gate length and channel thickness of less than 30 nm gate length and height 100 nm tall have been demonstrated. Functional devices at the 100 nm gate have Ion=191 /spl mu/A//spl mu/m, Vt=0.3 V Ioff =0.5 /spl mu/A//spl mu/m, SS=94 mV/decade. A different device with different implant dose and drive demonstrated Vt=0.15 V and SS=80mV/decade at Lgate=0.25 /spl mu/m.

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.

We have studied the oxidation of Si nanocrystals as a function of oxidizing ambient, temperature, time, and initial nanocrystal size using x-ray photoelectron spectroscopy, transmission electron microscopy, and energy-filtered transmission electron microscopy. Thicker oxide shells are obtained by oxidation in O2 ambient compared with NO ambient. Oxidation in O2 is observed to be self-limiting at temperatures below the viscoelastic temperature of SiO2 because of compressive stress normal to the SiO2/Si interface, which retards the surface oxidation rate. Oxidation in NO also results in self-limiting oxidation due to the incorporation of N at the Si/SiOx interface. This N-rich interfacial layer acts as an effective barrier against oxidant diffusion and also blocks the reaction sites on the Si surface. Therefore, NO oxidation is successful in slowing further oxidation of Si cores, even in a severe oxidizing ambient such as O2 at 1050 °C.

We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).

We report a 100 nm modular bulk CMOS technology platform with multi Vt and multi gate oxide integrated transistors that enables device and circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing and power down/reduction) for low standby power (LSP), high performance (HP), high speed (HS), and RF/analog system on chip (SoC) applications. The transistor performances are comparable to or better than recently reported data at the 100 nm technology node. This technology also features an all-layer copper/low-k (<3.0) interlayer dielectric (ILD) backend for speed improvement and dynamic power reduction (S. Parihar et al., Proc. IEDM, 2001).

In this report, a high performance silicon-on-insulator (SOI) transistor for the 100 nm CMOS technology node is presented. Partially depleted (PD) transistors were fabricated in a 1000 /spl Aring/-thick silicon film with gate lengths down to 45 nm, using a 16 /spl Aring/ nitrided gate oxide. At an operating voltage of 1.2 V, self-heated drive currents of 940 /spl mu/A//spl mu/m and 460 /spl mu/A//spl mu/m were achieved at 20 nA//spl mu/m for NMOS and PMOS respectively. Floating body effects (FBE) were minimized by special diode junction engineering to achieve maximum overall performance. A measured median stage delay of 6 ps was achieved on an inverter-fan-out-1 ring oscillator at 1.3 V at a total N+P leakage of 30 nA//spl mu/m. The exceptional AC performance of this technology is among the highest reported in the literature at this low transistor leakage and operating voltage.

MOSFETs with a zirconium dioxide (ZrO/sub 2/) gate dielectric and poly-silicon gate were fabricated using a low temperature CMOS process. Well-behaved transistor characteristics were obtained for devices with sizes of 14 /spl mu/m/spl times/1.4 /spl mu/m or smaller. Devices 14 /spl mu/m/spl times/14 /spl mu/m or larger were found to be nonfunctional due to the formation of Zr-silicide at the polySi-gate/Zr0/sub 2/ interface. In this paper, we present results on the electrical and physical characterization.

In recent years, the availability of focused ion beam (FIB) milling systems has given a much-needed boost for transmission electron microscopy (TEM) as a technique for site-specific analysis. Much progress has been made in the area of site-specific cross-sectional and planar TEM sample preparation techniques. However, a continuing need exists to reduce the sample preparation time, in order to improve TEM cycle time for better support of process development, yield improvement and production in a high-volume industrial environment. Thus, a faster TEM sample preparation technique is always desirable to meet this demand. A new approach to TEM sample preparation is described in this paper. Following the new approach developed in the present work, one can prepare on a single TEM grid at least two different cross-sectional samples of site-specific device structures or up to four different cross-sectional samples of blanket films. Two different samples, each containing an area of interest near the center, are cleaved or cut to a width of about 1.25 mm; these samples may be from two separate locations of a wafer, or from two different wafers where TEM analyses are required.

Critical dimensions in advanced semiconductor devices are now such that a significant fraction of some structures is contained within the thickness of a TEM foil. An important example is the vias used in multilevel metallization to interconnect transistors and other structures. Current generation vias have a diameter of 300 nm, and vias in devices under development are targeted at 180 nm. These dimensions are to be compared to the thickness of a TEM foil, which may be ∼50 nm. Vias are typically fabricated by etching holes in a dielectric layer, then depositing into these holes a barrier metal, such as Ta, followed by a Cu seed layer and finally Cu fill. Critical to via processing reliability are the thicknesses of barrier and seed layers. A TEM cross section of such a via will contain sharply curved layers which, when seen in projection, will lead to inaccurate measurement of layer thicknesses. Ordinary plan view preparation of these vias avoids this projection problem, but uncertainty is introduced in the height at which the via is sectioned.We have developed an angled plan view (APV) FIB preparation technique that allows accurate measurement of barrier and seed thicknesses at discrete heights from bottom to top of a via.

The compatibility of metallic titanium nitride (TiN) as a gate electrode on TiO2 and Ta2O5 gate dielectrics is investigated by rapid thermal annealing (RTA). The electrical and physical properties are characterized using I–V measurements and transmission electron microscopy. TiN/TiO2 capacitors are electrically stable up to at least 800 °C for 90 s. However, the leakage density for TiN/Ta2O5 capacitors is increased by an 850 °C, 60 s RTA. Both TiN/TiO2 and TiN/Ta2O5 capacitors display a large increase in leakage density after a 1025 °C, 20 s RTA.

Carbon and hydrogen free tetranitratotitanium was synthesized, which is believed to thermally decomposed primarily as: Ti(NO3)4→TiO2+4NO2+O2. The by-products of the thermal decomposition of tetranitratotitanium, which include NO2 and O2, may possibly provide a robust ultrathin tunnel interfacial layer. Due to the hydrogen free nature of thermolysis, N2O may form an oxynitride layer which has been shown to produce thermal oxynitrides with higher quality than NH3-based nitride oxides. Unlike titanium tetrakis isopropoxide (TTIP) deposited films, the interface state density more closely follows the “U” shape characteristic of conventional thermal SiO2/Si interfaces. The integrated interface state density is considerably less for the film annealed at higher temperature, which should produce considerably higher inversion layer mobilities. This improvement of the interface, compared to TTIP deposited films, is believed to be due to the elimination of water vapor from the deposition ambient.

The recent introduction of dual inlaid Cu and oxide based interconnects within sub-0.25μm CMOS technology has delivered higher performance and lower power devices. Further speed improvements and power reduction may be achieved by reducing the interconnect parasitic capacitance through integration of low-k interlevel dielectric (ILD) materials with Cu. This paper demonstrates successful multi-level dual inlaid Cu/low-k interconnects with ILD permittivities ranging from 2.0 to 2.5. Integration challenges specific to inorganic low-k and Cu based structures are discussed. Through advanced CMP process development, multi-level integration of porous oxide materials with moduli less than 0.5 GPa is demonstrated. Parametric data and isothermal annealing of these Cu/ low-k structures show results with yield comparable to Cu/oxide based interconnects.