Memristive self-organizing networks based on Agnanowires exhibit stochastic dynamics that can be described by a jump-diffusion Langevin equation driven by a Wiener process and a homogeneous compound Poisson process with Pareto distributed jump amplitudes. The Langevin equation models the evolution of the network memory state arising from the stochastic formation and rupture of multiple spatially distributed junctions. Continuous fluctuations and discrete switching events are represented by the diffusive and jump components of the equation, respectively, with the latter accounting for the observed heavy tailed statistics and the broad range of switching-event magnitudes. We develop and validate a SPICE-compatible stochastic compact model that captures the resulting network dynamics using the Method of Elementary Solvers (MES). A term by-term analysis of the memory-state equation facilitates the interpretation of the underlying stochastic dynamics. The compact model enables self-organizing nanowire networks to be incorporated as reusable SPICE subcircuits for circuit-level simulation. The underlying methodology is readily extendable to other systems governed by similar jump-diffusion stochastic dynamics.
A persistent challenge lies in developing electro active materials for next-generation supercapacitor applications that exhibit both high power and energy densities. Herein, we report a novel ball milling technique for the synthesis of Cu2SnSe3 and its application as a redox-active material to enhance supercapacitor performances. The film's uniformity and compactness are confirmed by the FESEM and HRTEM studies, which also shows a notable decrease in voids and grain dispersion. The XPS and XRD spectra further confirm the successful growth of Cu2SnSe3. When the scan rate is 2 mV/s, the Cu2SnSe3-based electrode has a remarkable capacitance of 711.77 F/g. Brilliant overall performance is further demonstrated by the asymmetric supercapacitor built with Ni foam-supported Cu2SnSe3 for the positive electrode and bio-waste activated porous carbon for the negative electrode. The Cu₂SnSe₃-based device offers a specific capacitance of 186.86 F/g when the current density is 5 mA/cm2 with an energy density as high as 125.61 Wh/kg and power density of 550 W/kg. Therefore, this work offers an advanced strategy for synthesizing ternary metal chalcogenides with good electrochemical performances for asymmetric supercapacitors.
Processing-in-memory (PIM) has emerged as an effective solution to address the von Neumann bottleneck in edge-AI accelerators. However, state-of-the-art (SoTA) digital PIM designs suffer from limited compute density due to bulky bit cells and transistor-intensive adder trees, thereby restricting scalability and energy efficiency. This work presents RM-DPU, a resource-multiplexed digital PIM unit featuring a dual-port 5T SRAM latch with shared 2T AND logic, achieving a per-bit multiplication cost of 5.25T and up to 56% transistor reduction over SoTA designs. In addition, a Transistor-Reduced 2D Interspersed Adder Tree (TRAIT) combining FA-7T and PG-FA-26T reduces power consumption by up to 21.35% and improves energy efficiency by 59% compared to conventional 28T RCA structures. Furthermore, the proposed CIA2M scheme enables run-time accuracy-latency trade-offs without requiring error-correction circuitry. The 16 Kb REP-DPIM macro achieves up to 1.72 TOPS throughput and 348.86 TOPS/W energy efficiency in 65 nm CMOS, while maintaining 96.85% Quality of Result (QoR) for ResNet-18 and VGG-16 on CIFAR-100 with 30% pruning. These results demonstrate that RM-DPU provides a scalable and energy-efficient solution for next-generation edge-AI accelerators.
This study presents the first detailed exploration of the DC and analog/RF performance of a new Junctionless Multi Bridge Dielectric-Insulator embedded Nanosheet FET, termed as JL MBDI-NSFET. A SiO2 dielectric insulator is integrated at the center of each channel in a vertically stacked NSFET structure to form this new device architecture. Its performance is then benchmarked against a conventional JL MB-NSFET, resulting in an acceptable subthreshold swing (SS) of 71.40 mV/dec and a reduction in OFF-current (IOFF) of about 74.12% from the TCAD simulation results. Additionally, the stacking trade-offs of the proposed device are examined. It is found that while the ON current (ION) significantly improves by 140.6% at S3 compared to S1, the output conductance (gd), transconductance frequency product (TFP), cut-off frequency (fT), and delay (τ) decrease by roughly 32.7%, 5.99%, 13.33%, and 19.55%, respectively. To address the existing trade-off, the effects of the gate length (LG) and dielectric insulator thickness (TDI) on DC performance have subsequently been assessed. Moreover, LG scaling at the analog/RF level is also investigated. Lastly, the circuit-level analysis is reviewed, confirming the viability of the proposed NSFET, which outperforms FinFET and GAA in terms of speed, power, and performance.
