The Belle II experiment operates at high luminosity, where an increasing beam-induced background imposes stringent demands on the hardware Level-1 trigger system, which must operate under tight latency and bandwidth constraints. To achieve online data reduction within the Level-1 trigger system, we have developed a hit-filtering algorithm based on the lightweight Interaction Network architecture. In this work, we present a hardware-aware model-compression workflow for this hit-filtering algorithm targeting deployment on FPGA devices within the Belle II trigger system. The network is adapted to the detector and trigger conditions through model-size and graph-size reduction, low-precision (4 bit) fixed-point arithmetic, and unstructured pruning. We assess the resulting design using the total number of bit operations as a hardware-aware computational complexity metric. Using this metric, we identify a configuration that decreases this cost by more than two orders of magnitude relative to the full-precision reference implementation. This reduction is achieved while preserving performance close to the reference model in terms of hit efficiency and background rejection, as indicated by only a modest decrease in the AUC score from 97.4 to 96.8, evaluated on Belle II collision data.

Graph neural networks are increasingly adopted in trigger systems for collider experiments, where strict latency and throughput constraints render deployment on embedded platforms challenging. As detectors move towards higher granularity, the number of inputs per inference increase and FPGA-only solutions face resource bottlenecks. This work presents an end-to-end demonstrator for the real-time deployment of a dynamic Graph Neural Network for the Belle II electromagnetic calorimeter hardware trigger on the AMD Versal VCK190, leveraging both FPGA fabric and AI Engine tiles. We develop a Python-based semi-automated design flow covering operator fusion, partitioning, mapping, spatial parallelization, and kernel-level optimization. Our design achieves a throughput of 2.94 million events per second at an end-to-end latency of 7.15 microseconds. Compared to the FPGA-only baseline, this represents a 53

Machine learning algorithms are being used more frequently in the first-level triggers in collider experiments, with Graph Neural Networks pushing the hardware requirements of FPGA-based triggers beyond the current state of the art. To meet the stringent demands of high-throughput and low-latency environments, we propose a concept for latency-optimized preprocessing of sparse sensor data, enabling efficient GNN hardware acceleration by removing dynamic input sparsity. Our approach rearranges data coming from a large number of First-In-First-Out interfaces, typically sensor frontends, to a smaller number of FIFO interfaces connected to a machine learning hardware accelerator. In order to achieve high throughput while minimizing the hardware utilization, we developed a hierarchical sparsity compression pipeline optimized for FPGAs. We implemented our concept in the Chisel design language as an open-source hardware generator. For demonstration, we implemented one configuration of our module as preprocessing stage in a GNN-based first-level trigger for the Electromagnetic Calorimeter inside the Belle II detector. Additionally we evaluate latency, throughput, resource utilization, and scalability for a wide range of parameters, to enable broader use for other large scale scientific experiments.

Neuromorphic computing utilizes bio-inspired, sparse, event-based processing to facilitate high-speed and low-power computation, making it very promising for embedded hardware. Specifically, only the synapses and neurons of a neural network that receive an input are computed. Therefore, when interfacing with such neuromorphic systems, data is either converted into an event-based representation or directly received from event-based sensors. However, due to high fluctuations in the incoming event stream, the required hardware resources vary accordingly. This variability makes it challenging to guarantee execution time and power consumption. To address this issue, we propose an adaptive buffering method, that acts as a passive filtering mechanism when an event burst occurs. We compare this method with other single- and multiple-buffering schemes with limited sizes to store incoming event data. The buffering schemes are tested on spiking neural networks, and we evaluate their impact on the classification accuracy and the number of executed synaptic operations for three event-based datasets. Depending on the buffering scheme used, it is possible to reduce the number of channels that provide input to 35

Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural networks. From this trend arises the need for high-performance hardware exhibiting predictable timing behavior. While state-of-the-art real-time hardware often suffers from limited memory and compute resources, modern AI accelerators typically lack the crucial predictability due to memory interference. We present a new hardware architecture to bridge this gap between performance and predictability. The architecture features a multi-core vector processor with predictable cores, each equipped with local scratchpad memories. A central management core orchestrates access to shared external memory following a statically determined schedule. To evaluate the proposed hardware architecture, we analyze different variants of our parameterized design. We compare these variants to a baseline architecture consisting of a single-core vector processor with large vector registers. We find that configurations with a larger number of smaller cores achieve better performance due to increased effective memory bandwidth and higher clock frequencies. Crucially for real-time systems, execution time fluctuation remains very low, demonstrating the platform's time predictability.

The commissioning and operation of future large-scale scientific experiments will challenge current tuning and control methods. Reinforcement learning (RL) algorithms are a promising solution thanks to their capability of autonomously tackling a control problem based on a task parameterized by a reward function. The conventionally utilized machine learning (ML) libraries are not intended for microsecond latency applications, as they mostly optimize for throughput performance. On the other hand, most of the programmable logic implementations are meant for computation acceleration, not being intended to work in a real-time environment. To overcome these limitations of current implementations, RL needs to be deployed on-the-edge, i.e. on to the device gathering the training data. In this paper we present the design and deployment of an experience accumulator system in a particle accelerator. In this system deep-RL algorithms run using hardware acceleration and act within a few microseconds, enabling the use of RL for control of ultra-fast phenomena. The training is performed offline to reduce the number of operations carried out on the acceleration hardware. The proposed architecture was tested in real experimental conditions at the Karlsruhe research accelerator (KARA), serving also as a synchrotron light source, where the system was used to control induced horizontal betatron oscillations in real-time. The results showed a performance comparable to the commercial feedback system available at the accelerator, proving the viability and potential of this approach. Due to the self-learning and reconfiguration capability of this implementation, its seamless application to other control problems is possible. Applications range from particle accelerators to large-scale research and industrial facilities.

As particle physics detectors grow in scale, High Energy Physics experiments must process ever-increasing data volumes. Level-1 trigger systems, implemented on Field-Programmable Gate Arrays and increasingly using neural-network algorithms, filter this data in real time. However, their proximity to the interaction point exposes them to radiation, which can corrupt outputs, stall processing pipelines, or damage hardware, with significant financial and scientific consequences. In this work, we present the first Register Transfer Level fault-injection study of a deployed Level-1 hardware neural-network trigger, GNN-ETM in the Belle II trigger system. We target three failure modes most consequential to a real-time trigger pipeline: deadlocks, timeouts, and packet-integrity violations. Through two complementary campaigns, we inject 1 442 840 Single-Event Upsets across 211 245 signals. We find a monitoring asymmetry in the existing verification infrastructure and propose inter-stage liveness monitoring as a more accurate alternative to output-only observation, showing that Mean Time To Failure estimates from the two approaches differ by up to 78.7

Spatiotemporal information is at the core of diverse sensory processing and computational tasks. Feed-forward spiking neural networks can be used to solve these tasks while offering potential benefits in terms of energy efficiency by computing event-based. However, they have trouble decoding temporal information with high accuracy. Thus, they commonly resort to recurrence or delays to enhance their temporal computing ability which, however, bring downsides in terms of hardware-efficiency. In the brain, dendrites are computational powerhouses that just recently started to be acknowledged in such machine learning systems. In this work, we focus on a sequence detection mechanism present in branches of dendrites and translate it into a novel type of neural network by introducing a dendrocentric neural network, DendroNN. DendroNNs identify unique incoming spike sequences as spatiotemporal features. This work further introduces a rewiring phase to train the non-differentiable spike sequences without the use of gradients. During the rewiring, the network memorizes frequently occurring sequences and additionally discards those that do not contribute any discriminative information. The networks display competitive accuracies across various event-based time series datasets. We also propose an asynchronous digital hardware architecture using a time-wheel mechanism that builds on the event-driven design of DendroNNs, eliminating per-step global updates typical of delay- or recurrence-based models. By leveraging a DendroNN's dynamic and static sparsity along with intrinsic quantization, it achieves up to 4x higher efficiency than state-of-the-art neuromorphic hardware at comparable accuracy on the same audio classification task, demonstrating its suitability for spatiotemporal event-based computing. This work offers a novel approach to low-power spatiotemporal processing on event-driven hardware.

We present a hardware-accelerated hit filtering system employing Graph Neural Networks (GNNs) on Field-Programmable Gate Arrays (FPGAs) for the Belle II Level-1 Trigger. The existing track trigger exhibits reduced efficiency, in particular for short and endcap region tracks, due to its requirement of aligned hits in the majority of detector layers. An efficient hit filter enables the subsequent track trigger to operate with relaxed requirements, allowing higher track finding efficiency without increasing the Level-1 trigger rate. The proposed GNN system exploits spatial and temporal correlations among sense wire hits for detector-level background suppression. The network is optimized for high-throughput hardware operation via quantization, pruning, and static graph-building. Sector-wise spatial parallelization permits scaling to full-detector coverage while satisfying Belle II latency and throughput requirements. At 32 MHz throughput and sub-microsecond latency, the system achieves an offline-validated 83 % background hit rejection at 95 % signal hit efficiency. This work demonstrates scalable, low-latency GNN-based hit filtering on FPGAs for real-time data reduction in high-luminosity collider environments.

This paper presents a programmable RFSoC-based system to emulate multiple-input multiple-output (MIMO) antenna systems used during the testing and prototyping phase of radar and communication applications. The emulator can be used to simulate complex antenna configurations in a laboratory environment, without the need for outdoor tests in a controlled and reproducible environment. It is implemented on a Xilinx ZCU216 evaluation board that provides up to 16 phase-coherent analog output channels. The ability of our antenna emulator to accurately replicate different antenna configurations is verified using a hardware-in-the-loop (HIL) setup simulating a direction of arrival (DoA) scenario. The measured results closely matched theoretical expectations, demonstrating the system’s functionality and practical applicability. Future improvements aim to enable the emulation of more extensive and complex scenarios, broadening the antenna emulator’s application scope.

The increasing throughput demands in real-time systems and the consolidation of functionality on few, highperformance platforms are driving a shift towards parallel architectures. A key challenge for multicore real-time systems is the interference from contention for access to shared memory. Phased execution approaches address this challenge by restricting shared memory access to mutually exclusive memory phases, while computation is limited to memories local to each core. However, the complexity of managing and scheduling said memory phases hinders the adoption of phased execution in real-time applications. To address this challenge, we propose a model-based deployment methodology that automates the process of adapting applications to phased execution. We present an integrated tool-based deployment process that extends the application through the necessary memory phases and provides a runtime environment to orchestrate execution on the target hardware platform. Our approach requires minimal changes to the application implementation since the deployment tool directly extracts the required information from the generated application binaries. We validate our methodology using an avionics case study on a RISC-V multicore system, showcasing its key components and principles of operation.

Convolutional Neural Networks (CNNs) have become an essential tool in the domain of vision processing. However, dedicated accelerators are needed for energy-efficient execution of these networks, especially for embedded devices with tight energy constraints. Integrating multiple of these accelerators via chiplets promises a way to scale up the performance of these emerging systems by partitioning a neural network across multiple accelerators. This approach enables the execution of different layers on an accelerator with the best-suited dataflow. However, partitioning a neural network is a non-trivial task, especially when different accelerator architectures must be considered. In this paper, we propose our framework DSEParted, which automates the co-design of network partitioning and hardware architecture optimization. It employs a hierarchical optimization approach to gradually reduce the number of design candidates until an optimal system configuration is found for a partitioned computation of a neural network. We demonstrate that our framework can design a system that, for GoogLeNet, reduces latency by 22.5% when optimizing for latency. In addition, when optimizing for energy, it reduces the system area by 7.9%, with no impact on latency or energy compared to a baseline system. Further, we show that our partitioning-aware pruning strategy can reduce the EDP of the system by up to 49.7% in the case of ResNeXt-50, compared to a strategy that only optimizes the accelerators individually. Through the provided information, designers receive feedback on the efficiency of the full system at an early development stage. Our work is available open source(1).

Spiking neural networks (SNNs), inspired by biological brains, use discrete spikes for communication, offering potential advantages in energy efficiency and temporal processing. These properties make them attractive for low-power, real-time control, but optimizing their structure and parameters is challenging. This work investigates the impact of spatial embedding on recurrent SNN performance and efficiency in continuous control tasks. We evolve SNNs with neurons positioned in a 3D Euclidean space, where connection probabilities and strengths decrease with distance. A genetic algorithm optimizes neuron parameters, connection weights, and network topology. Evaluating various spatial embeddings (none, 1D, 2D, and 3D) across multiple reinforcement learning environments, we find that spatially embedded networks outperform non-embedded counterparts within our framework. We also find that the 2D embedding generally achieves the best performance. Spatial embedding also leads to highly sparse networks, with over 95

The execution of diverse machine learning (ML) functionality on centralized automotive systems has dynamic execution characteristics. This includes uniform release characteristics as well as spikes in utilization of the deployed accelerators, during which functional constraints still need to be met, albeit at a reduced confidence in the result. Existing methods address this problem with dynamic rescaling or scheduling of anytime neural networks. Dynamic rescaling is not available for most pretrained neural networks, and existing work either do not support heterogeneous execution units or incur a high timing overhead. We introduce our open-source tool CH2AI to solve this challenge. CH2AI extends existing work by the support for heterogeneous execution units and a streamlined execution. CH2AI supports the generation of anytime neural networks from existing neural networks without the need to retrain the original network and the scheduling of these anytime neural networks onto heterogeneous execution units. Our evaluation includes an analysis of timing overheads, a timeliness analyses, as well as a tradeoff analysis between accuracy and (over) utilization. We observed a timing overhead between 2.1% and 7.2% for our tested ML models. For an (over) utilization of 250%, we observed timeliness of up to 99% for uniform task releases and between 70% and 85% for random task releases, depending on the used model. We preserved the accuracy in a 15% range for utilization spikes of up to 250%.

Graph-based Point Cloud Networks (PCNs) are powerful tools for processing sparse sensor data with irregular geometries, as found in high-energy physics detectors. However, deploying models in such environments remains challenging due to stringent real-time requirements for both latency, and throughput. In this work, we present a deeply pipelined dataflow architecture for executing graph-based PCNs on FPGAs. Our method supports efficient processing of dynamic, sparse point clouds while meeting hard real-time constraints. We introduce specialized processing elements for core graph operations, such as GraVNet convolution and condensation point clustering, and demonstrate our design on the AMD Versal VCK190. Compared to a GPU baseline, our FPGA implementation achieves up to 5.25x speedup in throughput while maintaining latencies below 10 μs, satisfying the demands of real-time trigger systems in particle physics experiments. An open-source reference implementation is provided.

The increase of heterogeneous AI accelerators, particularly in edge computing, creates significant challenges for building unified and scalable distributed acceleration systems. Existing approaches often lack support for diverse hardware types across multiple nodes, limit scalability, or introduce significant communication overheads. This paper introduces a novel service-oriented infrastructure concept to overcome these limitations, enabling management of distributed, heterogeneous AI accelerators. The proposed architecture features three core modules: a versatile Model Database supporting various formats and artifacts, hardware-specific Runners acting as execution agents, and a central Scheduler for system-aware task allocation. Key contributions include: 1) A conceptual framework for truly distributed, heterogeneous AI acceleration services, contrasting with single-node or vendor-locked solutions; 2) A modular design enabling extensibility and seamless lifecycle management crucial for long-term edge deployments; and 3) A design incorporating direct data communication paths between sources, accelerators, and sinks, aimed at reducing end-to-end latency compared to proxy-based or application-offloading methods by eliminating intermediate hops. The evaluations show advantages in edge scalability, hardware flexibility, built-in failure recovery, and latency advantages over existing solutions, with a reduction of up to 50

Ongoing trends of centralizing software functionality like Advanced Driver Assistance Systems in automotive vehicles have created the need for a centralized electric/electronic architecture with heterogeneous multicore processing systems on chip (MPSoCs). Standards such as ISO 26262 and ISO 21448 further necessitate measures to fulfill both real-time and safety requirements via real-time capable scheduling combined with redundancy measures.To be able to keep up with the increase in centralization and task complexity, a holistic scheduling approach is necessary. Fulfilling these standards, we propose HM2GP, a time-triggered phased execution model and scheduler for tasks with precedence constraints and arbitrary placement of execution phases. It also supports heterogeneous commercial of the shelf MPSoCs with multiple shared resources. This work provides a comprehensive framework that enables the scheduling and schedule optimization of complex task sets on centralized heterogeneous multicore platforms. We evaluate our work by introducing a real world case study and showing the generalization capabilities by scheduling synthetic task sets with HM2GP and related works. We observe no considerable runtime overhead compared to existing methods, while providing an extension to related works.

The Belle II experiment at the asymmetric-energy electron positron collider SuperKEKB aims to explore physics beyond the standard model (BSM). One of the widely discussed signatures for BSM are new, long-lived neutral particles, which decay into charged mesons or lepton pairs originating from a vertex usually far from the interaction point (IP) of the colliding beams. The current level-1 (L1) track trigger system is optimized for particles created at the IP and will thus reject, with high probability, such interesting events. This makes it necessary to develop a special L1 track trigger for events with a vertex displaced from IP, the Displaced Vertex Trigger (DVT). The pipelined and deadtime-free L1 trigger system of Belle II utilizes a set of FPGA boards to make rapid decisions within 5 microseconds. The new DVT will be operating in parallel with the existing track trigger systems. The DVT identifies events, where two tracks with opposite charge originate from a common vertex away from the IP. The track finding is done by a set of Hough transformations, each one assuming a certain track origin from a grid spanning the tracking volume. The correct vertex is then determined via a shape analysis of the Hough clusters, using neural networks. To manage the large number of track origin hypotheses, a pre-selection of candidates based on the properties of the Hough map is employed, which significantly reduces the required FPGA resources.

The ZuSE-KI-Mobil (ZuKIMo) research project presents a heterogeneous system-on-chip (SoC) designed for use in a variety of automotive and industrial edge applications. Implemented using GlobalFoundries (GF) 22-nm FD-SOI technology, the SoC features a modular architecture with a configurable, bit-serial, mixed-precision neural processing unit (NPU) core. This core can be adapted to different use cases, comes with a compact instruction set, and improves the performance of dilated convolutions. A hardware-accelerated, tunable image signal processor (ISP) hyperparameter pipeline reduces tuning time and increases detection confidence for AI tasks. The system also incorporates a selective, per-layer fault-tolerance mechanism and supports rapid prototyping via an Apache TVM-driven compiler flow and cycle-accurate simulation. The adaptable hardware generation process is designed with future chiplet-based scaling in mind, providing a flexible foundation for upcoming heterogeneous SoC designs.

The application of machine learning (ML) is becoming more widespread, with a growing number of use cases. The development of centralized data training and the exponential growth of data generation raise significant privacy and security concerns. To mitigate these issues, on-device transfer learning (TL) offers the ability for models to adapt to local data without relying on a cloud connection. TL can leverage the knowledge gained from pre-trained models, hence, accelerating the training process. In parallel, ML compilers have become an essential tool for deploying ML models on a wide range of hardware platforms. However, current ML compilers focus on optimizing inference, neglecting on-device TL that can address real-world challenges, such as model performance degradation and distribution shift. This article proposes a mixed-precision partitioning algorithm, which identifies optimal partitioning layers for retraining, and a general compilation approach, based on Apache TVM, that enables on-device TL for embedded systems. We provide performance measurements for embedded graphics processing units (GPUs), central processing units (CPUs), and an artificial intelligence (AI) accelerator, demonstrating a simplified deployment process for deep neural networks (DNNs) with integrated on-device training capabilities.