Unipolar junctionless transistors are thin-film, heavily doped (typically in the 10(19) cm(-3) range) semiconductor resistors with a gate electrode that controls the flow of current between source and drain. Device design is extremely simple as there are no PN junctions. Device operation relies on fully depleting the semiconductor using the workfunction of the gate material to turn the device off. When the device is turned on, current flows through the bulk of the thin film, and can be augmented by an accumulation current contribution. Junctionless transistors are characterized by reduced short-channel effects and present excellent subthreshold slope and low DIBL.

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

Silicon is by far the most widely used semiconductor material. It is abundant in earth’s crust and relatively easy to convert into a high-purity single crystal. Unlike some other semiconductor materials silicon is stable when heated at high temperature, and a well-behaved insulating and passivating material, silicon dioxide, can readily be grown on it. The excellent electrical and chemical properties of thermally grown SiO2 are probably the most important factor that has made silicon such a successful semiconductor material.

In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.

This paper analyzes the very strong SEU hardness of a 1k static random-access memory fabricated using the SOI/GAA technology, irradiated with a xenon ion beam at various angles of incidence. The memory has been shown to operate with a supply voltage as low as 2V while still presenting excellent SEU hardness. Since the different physical charge collection mechanisms are particularly slow in SOI devices, it is shown that collected and critical charges must be dynamically compared in order to determine the SEU threshold. A new approach is then proposed to evaluate the time-variable critical charge independently of the pulse shape generated by the incident ion, and a general analytical model is derived. Finally, predictions in good agreement with experimental data are obtained.

Various issues in SOI (silicon-on-insulator) CMOS technology are reviewed. In particular, it is pointed out that from a device standpoint, the `nice' properties of FD SOI MOSFETs, such as high saturation current and sharp subthreshold slope, are now overshadowed by unwanted floating substrate effects. The most serious of these is caused by the lateral bipolar, which causes snapback in long-channel devices. The snapback reduces to low BVDS in shorter-channel devices. There are indications that SOI may have a better BVDS than bulk for L<0.3 μm. The physics underlying hot-carrier degradation effects remains basically unresolved in thin-film SOI devices. At the circuit level, SPICE versions of SOI MOSFET models need to be commercially available, as well as cell libraries. ESD protection structures, using either diode or snapback transistors, have to be assessed

A first-order model for the temperature dependence of threshold voltage in thin-film silicon-on-insulator (SOI) n-MOSFETs is described. The temperature dependence of the threshold voltage of thin-film SOI n-channel MOSFETs is analyzed. Threshold voltage variation with temperature is significantly smaller in thin-film (fully depleted) devices than in thick-film SOI and bulk devices. The threshold voltage is shown to be dependent on the depletion level of the device, i.e. whether it is fully depleted or not. There exists a critical temperature below which the device is fully depleted, and above which the device operates in the thick-film regime.< >

Summary form only given. Anomalously sharp subthreshold slopes in fully depleted ultrathin SOI MOSFETs are discussed. The effect can be eliminated by control of the lower SOI interface charge condition. The temperature dependence of this effect is also discussed.<>

Two advantages of ultrathin (<or=1000 AA) silicon-on-insulator (SOI) films for MOSFETs that have not previously been reported are described. Compared to bulk FETs of similar dimensions are doping levels, the effects have been observed to give up to 35% increase in drain saturation current or transconductance. Both experimental data and modeling are discussed. It is noted that the kink effect is ab...

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4*10/sup 16/ cm/sup -3/, the drain saturation current in ultrathin SOI transistors is predicted to be approximately 40% larger than that of bulk structures. An increase of approximately 30% is seen in measurements made on devices in 1000-A SOI films.< >

Numerical simulation is used to show that potential and electric field distribution within thin, fully depleted SOI devices is quite different from that observed within thicker, partially depleted devices. Reduction of drain electric field and of source potential barrier brings about a dramatic decrease of kink effect.<>

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.

The properties that can be expected from thin-film silicon-on-insulator transistors are described. Simple qualitative modeling shows that improvements of different parameters, such as subthreshold slope, hot-electron effects, and short-channel effects, can be obtained when thin, fully depleted films are used. The potential advantages of using these devices for future small-geometry CMOS applications are highlighted.

This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.

MOS transistors and ring oscillators have been fabricated in thin (100 nm) SIMOX films. As has been theoretically predicted, no 'kink' effect is observed in the n-channel devices, the inverse subthreshold slope is lower than in bulk devices (70mV/decade against HOmV/decade in bulk), and the dependence of threshold voltage on gate length is much less pronounced than in the bulk.