A 4 x 4 single-flux-quantum (SFQ) network switch has been packaged and successfully demonstrated in a hybrid closed-cycle refrigerator (CCR) system at multigigabit data rates, Full operation of the packaged switch, with self-routing of 4-Gb/s data packets, was demonstrated using a 1-GHz address header decode. The switch is packaged on a superconducting multichip module (MCM) mounted on the 4.5-K stage of the CCR, On-chip asynchronous Josephson drivers and cooled GaAs preamplifers are used to amplify the SFQ outputs of the switch. The maximum operation bandwidth of the switch is currently limited by the asynchronous Josephson driver. New designs of the Josephson drivers, which have demonstrated operation at 10 Gb/s, are expected to enable switch operation at 10 Gb/s, The system is equipped with fiber-optical inputs and high-speed cryogenic photodetectors. The fiber-optic interfaces, RF packaging, and MCM packaging in the CCR system have demonstrated error-free operation at 10 Gb/s.

A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.

Ultra-low power and ultra-high speed single-flux-quantum electronics is an enabling near-term technology solution for petaflops-scale computers. The proposed Hybrid Technology Multi-threaded (HTMT) petaflops computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Petabits/s. Due to fundamental time-of-flight and power dissipation limitations of semiconductor ICs, superconductor ICs at an integration level of 100 k gates/cm/sup 2/ are proposed for the HTMT computation modules. In this paper, we discuss the manufacturability of superconductor-based computation modules, including the IC foundry process, packaging, and data link out of the cryopackage. We focus on the critical technical challenges that exist in each of these areas and present a technology roadmap to achieve the HTMT requirements.

A crossbar switch has been designed using Single Flux Quantum (SFQ) gates exclusively for all internal functions. A 4/spl times/4 prototype has been fabricated in our Nb process foundry with J/sub c/ of 2000 A/cm/sup 2/. We report on the design and performance of the switch and of an individual crosspoint element at high data rates (/spl ges/1 Gbps). A novel design of a double-edge-triggered dc/SFQ converter is discussed. The requirements for output amplification and on-chip versus off-chip amplifier issues will be presented.

Development of a reliable flipped chip mounting technique enables demonstration of high speed, complex digital circuits. Flip chip mounting has greatly reduced parasitic inductance compared to conventional wire bonding, and permits remounting of known good die onto multi-chip modules. Superconductive digital circuits have operated to 4.3 Gb/s in our custom test station. The circuit and carrier are fabricated using TRW's foundry process. The chips are flipped onto a superconducting coplanar carrier using a low temperature solder reflow process reported on at this conference. Testing is performed in a multi-GHz, flip contact, variable temperature probe. This test facility is capable of testing circuits to 12 Gb/s. We will describe the operation and performance of our circuits at high bit rates, and design improvements intended to facilitate operation at higher bit rates with improved yield. In addition, we will discuss the use of a logic simulation tool to analyze the output words, and pinpoint the gate or gates that failed to operate properly.

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.<>

We have systematically studies designs for Modified Variable Threshold Logic Gates (MVTL) in NbN within the framework of factorial analysis. Our goal is to attain optimized margin and fanout for 10 K operation. Significant parasitic inductances, associated with current crowding at junction vias, were measured and are found to affect the operating margin. We report the progression of designs, margin measurements and yield data for our 10 K circuits.< >

Demonstrating superconductive logic circuits at high speeds is crucial in gaining acceptance by potential users. We are taking an integrated approach toward demonstrating the potential of such circuits. Issues addressed include the effects that layout have upon a circuit and gate (particularly in scaling down the size of gates to increase density), testing limitations, designing for minimum crosstalk and ground ripple, and fundamental limitations to gate performance. In this paper, we report our progress in resolving and understanding these issues. Circuits such as shift registers were used to understand the influence of layout on performance, circuits such as gate chains and punchthrough detectors to explore fundamental gate limitations. We also report on signal processing circuits of several hundred gates tested at clock frequencies up to several hundred MHz and the relationship between these results and the fundamental gate performances.<>

We present the fabrication and electrical performance of an eight mask step, 2.5 x 2.5 mu m(2) minimum junction size, all refractory NbN integrated circuit process. NbN/MgO/NbN trilayers sputtered in situ are patterned by reactive ion etching to form Josephson tunnel junctions. A two-level dielectric process has been developed to ensure low defect densities. Sputtered molybdenum films form a resistor layer. NbN wire J(c) enhancement and improved step coverage have been achieved. This process has been used to successfully fabricate SQUID amplifier circuits, digital MVTL circuits, arrays of 256 SQUIDS, SFQ counters, and 4000 junction strings. We demonstrated NbN logic circuit operation above 10K.

We have built and demonstrated an all superconductive digital readout for use in an IR focal plane array sensor. High performance, ultralow power superconductive circuits perform the functions of low noise preamplification and analog to digital conversion. The superconductive readout was tested with a variety of detectors, including InSb, Si:As, and a thin film NbN superconducting detector. Light sources included a HeNe laser (0.6 micron), a CO2 laser (10 microns), and a blackbody (400 to 900 K). In each case, the detector and readout circuitry was assembled into a 2 inch diameter, 6 inch long test package cooled in a single dewar. We demonstrated the functionality of the detector/readout channel from input photons to output digital signal. The superconductive readout reported here used Nb-based circuits operating at 4 K. An NbN squid amplifier and detector have subsequently been demonstrated above 10 K. We discuss the extension of the entire digital readout to operating temperatures above 10 K.

A Josephson binary counter using single-flux quanta transitions of dc SQUID's has been fabricated using an eight-level NbN-based process. High-speed binary division has been demonstrated at 4.2 K, with single-cell counting observed at 60 GHz using the Josephson voltage-to-frequency relationship. Count rate was primarily limited by conservative process and design rules. The counter was designed for operation at 4.2 K. At 8-10 K, the beta-L of the SQUID's would not allow operation, though the junction characteristics were good.

Thin films of Y1Ba2Cu3O7−x (YBCO) with and without underlayers of SrTiO3 (STO) were deposited via pulsed laser deposition onto substrates of sapphire and silicon-on-sapphire (SOS) in a single vacuum step. The YBCO films with STO underlayers displayed better superconducting transitions than the YBCO films without underlayers, with zero-resistance temperatures of 86.5 and 75 K for films with underlayers on sapphire and SOS substrates, respectively. X-ray diffraction and secondary-ion mass spectroscopy have been used to explore the role played by the STO underlayer in improving film quality.