Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM).1'2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable.3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing.In this work, we assess mutltiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.

With the continuous shrink of design rules from 14nm to 10nm to 7nm, conserving process windows in a high volume manufacturing environment is becoming more and more difficult. Masks, scanners, and etch processes have to meet very tight specifications in order to keep defect, CD, as well as overlay within the margins of the process window. In this work, we study a design-based e-beam defect inspection technology for wafer level process window characterization and intra-field defect variability on 10nm logic devices. Due to high resolution, e-beam technology is the natural choice for review and/or detection of subtle pattern deviations, aka defects. The capability of integrating design information (GDS file) with defect detection, dimension measurement of critical structure, and defect classification provides added values for engineers to identify yield limiting systematic defects and to provide feedback to design.

As design rules for leading edge devices have shrunk to 1x nm size and below, device patterns have become sensitive to sub-10nm size defects. Additionally, defectivity and yield are now increasingly dominated by systematic patterning defects. A method for identifying and inspecting these hot spot (HS) locations is necessary for both technology development and High Volume Manufacturing (HVM). In order to achieve sufficient statistical significance across the wafer for a specific product and layer, a guided, high-speed e-beam inspection system is needed to cover a significant amount of high-volume hot spot locations for process window monitoring. In this paper, we explore the capabilities of a novel, high-throughput e-beam hot spot inspection tool, SkyScan (TM) 5000, on a 10nm back-end-of-line (BEOL) wafer patterned using a triple lithography-etch process. ASML's high-resolution, design-aware computational hot spot inspection is used to identify relevant hot spot locations, including overlay-sensitive patterns. We guide the e-beam tool to these Points of Interest (POI) and obtain experimental data from inspection of 430k wafer locations. The large amount of data allows detection of wafer-level and intra-field defect signatures for a large number of hot spot patterns.

EUV Lithography is aimed to be inserted into mainstream production for sub-20nm pattern fabrication. Unlike conventional optical lithography, frequent defectivity monitors (adders, repeaters etc.) are required in EUV lithography. Due to sub-20nm pattern and defect dimensions e-beam inspection of critical pattern areas is essential for yield monitor. In previous work we showed sub-10nm defect detection sensitivity1 on patterned resist wafers. In this work we report 8-10× improvement in scan rates of etched patterns compared to resist patterns without loss in defect detection sensitivity. We observed good etch transfer of sub-10nm resist features. A combination of smart scan strategies with improved etched pattern scan rates can further improve throughput of e-beam inspection. An EUV programmed defect mask with Line/Space, Contact patterns was used to evaluate printability of defects and defect detection (Die-Die and Die-Database) capability of the e-beam inspection tool. Defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability and were compared to previously obtained results on resist patterns.

Understanding the effect of defect sizes and their impact on EUV lithography is an ongoing challenge due to continued scaling of devices [1], [2]. The objective of this study is to assess printability of defects on post develop photoresist wafers and their detection capability with an electron beam inspection tool on EUV resist for various patterns (Line/Space, Contacts). Total capture of defects is an important factor for assessing printability on photoresist patterned wafers and monitoring process window. In this work, we present a comparison of Die to Die (reference to programmed defect to sites on wafer) and Die to Database (program defect sites on wafer to design). A programmed defect test mask is used to understand the impact of printing mask defects at multiple lithography levels (ex. gate, metal etc.) at 20 and 14nm technology ground rules. It is designed with both additive and subtractive features at defect sizes ranging from 30nm to 1nm. The defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability.

EUV lithography (EUVL) is the most promising solution for 16nm HP node semiconductor device manufacturing and beyond. The fabrication of defect free EUV mask is one of the most challenging roadblocks to insert EUVL into high volume manufacturing (HVM). To fabricate and assure the defect free EUV masks, electron beam inspection (EBI) tool will be likely the necessary tool since optical mask inspection systems using 193nm and 199nm light are reaching a practical resolution limit around 16nm HP node EUV mask. For production use of EBI, several challenges and potential issues are expected. Firstly, required defect detection sensitivity is quite high. According to ITRS roadmap updated in 2011, the smallest defect size needed to detect is about 18nm for 15nm NAND Flash HP node EUV mask. Secondly, small pixel size is likely required to obtain the high sensitivity. Thus, it might damage Ru capped Mo/Si multilayer due to accumulated high density electron beam bombardments. It also has potential of elevation of nuisance defects and reduction of throughput. These challenges must be solved before inserting EBI system into EUV mask HVM line. In this paper, we share our initial inspection results for 16nm HP node EUV mask (64nm HP absorber pattern on the EUV mask) using an EBI system eXplore® 5400 developed by Hermes Microvision, Inc. (HMI). In particularly, defect detection sensitivity, inspectability and damage to EUV mask were assessed. As conclusions, we found that the EBI system has capability to capture 16nm defects on 64nm absorber pattern EUV mask, satisfying the sensitivity requirement of 15nm NAND Flash HP node EUV mask. Furthermore, we confirmed there is no significant damage to susceptible Ru capped Mo/Si multilayer. We also identified that low throughput and high nuisance defect rate are critical challenges needed to address for the 16nm HP node EUV mask inspection. The high nuisance defect rate could be generated by poor LWR and stitching errors during EB writing of 64nm HP resist pattern. This result suggests we need further improvements not only in the EBI inspection system but also the patterning processes for 16nm HP node EUV masks.

Effectively patterning the intended design on the wafer for all possible geometries allowed by the design rule document is one of the most critical challenges for semiconductor manufacturing. Despite new lithography techniques like OPC, double patterning and the latest patterning simulation methods, and on-wafer evaluation using brightfield inspection and SEM review tools, patterning problems still occur and can result in a major delay in the qualification of a technology or product. Of particular concern are shorts and opens that cause product chip failure. Initial discovery of yield issues when a chip is being functionally tested is highly undesirable. A system for in-line, die to database (D2DB) comparison using E-beam inspection has been developed to address this risk. This system offers a substantial new line of defense against these patterning issues. The D2DB system is described along with a methodology for applying it for pattern fidelity inspection. Some examples illustrating the system operation are presented.

This paper proposes a combination use of e-beam inspection (EBI) for defect detection and CD Uniformity (CDU) measurement. The experiments are based on 14nm FinFET device manufactured on SOI substrate. A 5nm pixel size is utilized to perform hot spot inspection on SRAM pattern and N/P FET pattern after gate etching, spacer formation, and SiGe epitaxy process respectively. CDU measurement results match well with process split in gate etching and spacer formation process. Protrusion defect is detected after SiGe epitaxy process, and a dependency between protrusion defects with the thickness of spacer is found.

In this paper, we tested a novel methodology of measuring critical dimension (CD) uniformity, or CDU, with electron beam (e-beam) hotspot inspection and measurement systems developed by Hermes Microvision, Inc. (HMI). The systems were used to take images of two-dimensional (2D) array patterns and measure CDU values in a custom designated fashion. Because this methodology combined imaging of scanning micro scope (SEM) and CD value averaging over a large array pattern of optical CD, or OCD, it can measure CDU of 2D arrays with high accuracy, high repeatability and high throughput.

Fabrication of defect free EUV masks including their inspection is the most critical challenge for implementing EUV lithography into semiconductor high volume manufacturing (HVM) beyond 22nm half-pitch (HP) node. The contact to bit-line (CB) layers of NAND flash devices are the most likely the first lithography layers that EUV will be employed for manufacturing due to the aggressive scaling and the difficulty for making the pattern with the current ArF lithography.To assure the defect free EUV mask, we have evaluated electron beam inspection (EBI) system eXplore (TM) 5200 developed by Hermes Microvision, Inc. (HMI) [1]. As one knows, the main issue of EBI system is the low throughput. To solve this challenge, a function called Lightning Scan (TM) mode has been recently developed and installed in the system, which allows the system to only inspect the pattern areas while ignoring blanket areas, thus dramatically reduced the overhead time and enable us to inspect CB layers of NAND Flash device with much higher throughput.In this present work, we compared the Lightning scan mode with Normal scan mode on sensitivity and throughput. We found out the Lightning scan mode can improve throughput by a factor of 10 without any sacrifices of sensitivity. Furthermore, using the Lightning scan mode, we demonstrated the possibility to fabricate the defect free EUV masks with moderate inspection time.