Lithographic and pitch-multiplying spacer technologies are widely used to shrink interconnect periodicity within critical layers. This places significant burden on overlay and CD uniformity of the subsequently patterned vias to physically contact and electrically connect critical layers to the rest of the integrated circuit in a nearly defect-free and perfectly-consistent manner. We are evaluating the combination of EUV and DSA patterning technologies to meet this challenge and enable future technology nodes. The contact hole guide pattern is fabricated atop bilayer hardmask material by single-exposure EUV, surface-modified with telechelic polymer brush materials, and finally shrunk/rectified using self-assembled, lamella-forming polystyrene-block-polymethylmethacrylate (PS-b-PMMA). The nascent via pattern is then blanket exposed by DUV light and the photolyzed PMMA is selectively rinsed away. Here we study the process performance of DSA pattern wet etch chemistry and subsequent dry etch pattern transfer into bilayer hardmask material using both metrology and electrical yield measurements as evaluation criteria. In particular, the choice of wet etch solvation strength selective towards PMMA was varied from moderate (isopropanol, IPA) to good (acetic acid, AAc). Due to the ability of AAC to solubilize all covalently-untethered PMMA, regardless of molecular weight, the resulting average CD is wider and its local distribution is more uniform. In contrast, IPA is only capable of rinsing away the smallest PMMA fragments, resulting in relatively tighter bounds about the preferable blanket UV dose, and a smaller average CD and less-uniform local CD distribution. These morphological differences are confirmed by cross-sectional transmission electron micrographs. Brightfield inspection and inline electrical testing are used to compare relative defectivity and yield, respectively, to assess the potential impact on device performance for processes utilizing either solvent.

Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.

The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). Functional electrical testable Via-Chain structure is fabricated to verify the integrity of the proposed method. Through the analysis of the observed failure modes, the process is further improved. By validating DSA for such an important patterning element as metal cut, the DSA maturity can be further advanced and hopefully move DSA closer to HVM adoption.

Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in pursuance of meeting resolution targets and mitigating pattern collapse. In order to maintain the etch budget during hard mask open, the adhesion layer separating resist and hard mask must scale accordingly. We have reported a grafted polymer brush adhesion layer used in an ultrathin EUV patterning stack and demonstrated sub-36 nm pitch features with significant improvement over existing adhesion promotion techniques(1). This paper provided further understanding of this class of materials based on chemical characteristics. We first proposed a hypothesis of the adhesion mechanism, and probed key factors that could affect adhesion performance. The grafting kinetics study of polymer brush that contains different functional groups to the substrate shows grafting chemistry, time, and temperature are key factors that affect printing performance. We then conducted a systematic study to understand printing capability at various pitches with different resist thicknesses for different silicon-based substrates. By comparing the process window, we gained comprehensive understanding of the printing limits and failure modes with this approach. We provided a comparative study of a grafted adhesion layer vs. a conventional spin-on BARC type material, including defectivity and yield. Pattern transfer to hard mask with varied brush breakthrough time was conducted to understand the performance of polymer brush adhesion layer during pattern transfer.

The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). The combined effect of LCDU and centroid jittering will be discussed and compared to a hole shrink process using atomic layer deposition and spacer formation. The learning from this case study can provide perspectives that may not have been investigated thoroughly in the past. By including more important elements during DSA process development, such as metal cut, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

The drive to deliver increasingly powerful and feature-rich integrated circuits has made technology node scaling-the process of reducing transistor dimensions and increasing their density in microchips-a key challenge in the microelectronics industry. Historically, advances in optical lithography patterning have played a central role in allowing this trend to continue. Directed self-assembly of block copolymers is a promising alternative patterning technique that offers sub-lithographic resolution and reduced process complexity. However, the feasibility of applying this approach to the fabrication of critical device layers in future technology nodes has never been verified. Here we compare the use of directed self-assembly and conventional patterning methods in the fabrication of 7 nanometre node FinFETs, using an industrially relevant and high-volume manufacturing-compliant test vehicle. Electrical validation shows comparable device performance, suggesting that directed self-assembly could offer a simplified patterning technique for future semiconductor technology.

We report on the printability, mitigation and actinic mask level review of programmed substrate blank pit and bump defects in a EUV lithography test mask. We show the wafer printing behavior of these defects exposed with an NXE:3300 EUV lithography scanner and the corresponding mask level actinic review using the AIMS (TM) tool. We will show which categories of these blank substrate defects print on wafer and how they can be mitigated by hiding these defects under absorber lines. Furthermore we show that actinic AIMS (TM) mask review images of these defects, in combination with a simple thresholded resist transfer model, can accurately predict their wafer printing profiles. We also compare mask level actinic AIMS (TM) to top down mask SEM review in their ability to detect these defects.

In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

The use of EUV photomasks in a semiconductor manufacturing environment requires their periodic inspection to ensure they are continually free of defects that could impact device yield. Defects typically occur from fall-on particles or from surface degradation such as “haze”. The proposed use of a polycrystalline-based EUV pellicle to prevent fall-on particles would preclude periodic through-pellicle mask defect inspection using e-beam, as well as, DUV inspection tools (the pellicle is opaque at DUV wavelengths). Thus, to use these types of defect inspection tools would require removal of the EUV pellicle before inspection. After inspection, the pellicle would need to be re-attached and the mask re-qualified using a test wafer, thus causing expense and delays. While EUV-wavelength inspection tools could inspect through such a pellicle precluding the need to remove the pellicle, these tools are not likely to be available in the commercial marketplace for many years. An alternate EUV pellicle material has been developed that is semi-transparent to 193nm wavelengths, thus allowing through-pellicle inspection using existing ArF-based, or other 193nm wavelength mask inspection tools. This eliminates the requirement to remove the pellicle for defect inspection and the associated time and expense. In this work, we will conduct an initial evaluation of through-pellicle EUV mask defect inspection using an existing 193nm mask inspection tool. This initial evaluation will include durability of the pellicle to defect inspection, and impact of the pellicle on inspection tool performance.

Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM).1'2 A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable.3, 4 Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing.In this work, we assess mutltiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.

The detection of EUV mask adder defects has been investigated with an optical wafer defect inspection system employing a methodology termed Die-to-"golden" Virtual Reference Die (D2VRD). Both opaque and clear type mask absorber programmed defects were inspected and characterized over a range of defect sizes, down to (4x mask) 40 nm. The D2VRD inspection system was capable of identifying the corresponding wafer print defects down to the limit of the defect printability threshold at approximately 30 nm (1x wafer). The efficacy of the D2VRD scheme on full chip wafer inspection to suppress random process defects and identify real mask defects is demonstrated. Using defect repeater analysis and patch image classification of both the reference die and the scanned die enables the unambiguous identification of mask adder defects.

EUV lithography is one of the main candidates for enabling the next generation of devices, primarily by enabling a lithography process that reduces complexity, and eventually, cost. IBM has installed the latest tool sets at the IBM EUV Center of Excellence in Albany to accelerate EUV lithography development for production use. Though the EUV cluster is capable of enabling the pitch requirements for the 7nm node, the dimensions in question represent a new regime in defectivity. Additionally, new classes of patterning materials are being explored, for which there is very little known up-front regarding known defect mechanisms. We will discuss the baseline cluster performance and the improvement strategy in terms of defectivity and pattern collapse in this paper by utilizing coater/developer techniques based on the new platform.

The cleaning requirements for EUV masks are more complex than optical masks due to the absence of available EUV-compatible pellicles. EUV masks must therefore be capable of undergoing more than 100 cleaning cycles with minimum impact to lithographic performance. EUV masks are created on substrates with 40 multilayers of silicon and molybdenum to form a Bragg reflector, capped with a 2.5nm-thick ruthenium layer and a tantalum-based absorber; during usage, both ruthenium and absorber are exposed to the cleaning process. The CrN layer on the backside is used to enable electrostatic clamping. This clamp side must also be free of particles that could impact printing and overlay, and particles could also potentially migrate to the frontside and create defects. Thus, the cleaning process must provide decent particle removal efficiencies on both front-and backside while maintaining reflectivity with minimal surface roughness change. In this paper, we report progress developing a concurrent patterned-side and clamped-side cleaning process that achieves minimal reflectivity change over 120 cleaning cycles, with XPS and EDS indicating the presence of ruthenium after 125 cleaning cycles. The change in surface roughness over 100 cleaning cycles is within the noise (0.0086nm) on a mask blank, and SEM inspection of 100nm and 200nm features on patterned masks after undergoing 100 cleaning cycles show no indications of ruthenium pitting or significant surface damage. This process was used on test masks to remove particles from both sides that would otherwise inhibit these masks from being used in the scanner.

EUV Lithography is aimed to be inserted into mainstream production for sub-20nm pattern fabrication. Unlike conventional optical lithography, frequent defectivity monitors (adders, repeaters etc.) are required in EUV lithography. Due to sub-20nm pattern and defect dimensions e-beam inspection of critical pattern areas is essential for yield monitor. In previous work we showed sub-10nm defect detection sensitivity1 on patterned resist wafers. In this work we report 8-10× improvement in scan rates of etched patterns compared to resist patterns without loss in defect detection sensitivity. We observed good etch transfer of sub-10nm resist features. A combination of smart scan strategies with improved etched pattern scan rates can further improve throughput of e-beam inspection. An EUV programmed defect mask with Line/Space, Contact patterns was used to evaluate printability of defects and defect detection (Die-Die and Die-Database) capability of the e-beam inspection tool. Defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability and were compared to previously obtained results on resist patterns.

Understanding the effect of defect sizes and their impact on EUV lithography is an ongoing challenge due to continued scaling of devices [1], [2]. The objective of this study is to assess printability of defects on post develop photoresist wafers and their detection capability with an electron beam inspection tool on EUV resist for various patterns (Line/Space, Contacts). Total capture of defects is an important factor for assessing printability on photoresist patterned wafers and monitoring process window. In this work, we present a comparison of Die to Die (reference to programmed defect to sites on wafer) and Die to Database (program defect sites on wafer to design). A programmed defect test mask is used to understand the impact of printing mask defects at multiple lithography levels (ex. gate, metal etc.) at 20 and 14nm technology ground rules. It is designed with both additive and subtractive features at defect sizes ranging from 30nm to 1nm. The defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability.

For projection printing imaging systems with fixed or restricted illumination modes, pupil filters may enhance imaging for select features by blocking rays of light that negatively contribute to imaging. A method to design pupil filters for the optimum printing of a select feature type and size is presented. With this method, a series of pupil filters have been developed and are being tested to enhance the resolution of the Albany Alpha Demo Tool (ADT, 0.25NA) in order to enable resist and process development at feature sizes relevant to the 10 and 7nm nodes. By only allowing light to propagate to the wafer that positively contributes to imaging, six filters have been custom designed to optimize printing of the following sub-resolution feature types and sizes: 22 and 19 nm HP lines, 24 and 21 nm HP contacts, and 27x22 nm HP rectangular contacts. Development and installation of enabling hardware on the scanner is complete, six filters have been manufactured and imaging in resist has validated the concept. Over 20% improvement in tool resolution has been achieved for 22nm HP lines, allowing resist process development for NXE3300 conditions on the ADT. This paper discusses the theory behind the filter designs, the experimental in-resist evaluations, and other aspects of the development, to include challenges caused by the filters with slit uniformity, stray light, and reticle alignment.

The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k1-value when printing with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography technology as seen from an end-user perspective is summarized and the current values of the most important metrics for each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into production at the 14 nm technology node.

This paper will describe the development, qualification, monitoring, and integration into a production environment of the world's first fully programmable illuminator for optical lithography. FlexRay (TM), a programmable illuminator based on a MEMs multi-mirror array that was developed for TWINSCAN XT:19x0i and TWINSCAN NXT series ASML immersion scanners, was first installed in January 2010 at Albany Nanotech, with subsequent tools installed in IBM's East Fishkill Manufacturing facility. After a brief overview of the concept and benefits of FlexRay, this paper will provide a comprehensive assessment of its reliability and imaging performance. A CD-based pupil qualification (CDPQ) procedure will be introduced and shown to be an efficient and effective way to monitor pupil performance. Various CDPQ and in-resist measurement results will be described, offering convincing evidence that FlexRay reliably generates high-quality pupils and is well suited for high volume manufacturing at lithography's leading edge.