We investigate the threshold voltage $(\boldsymbol{V}_{\text{th }}$) distribution of a 176-layer TLC vertical NAND (VNAND) flash memory by experimentally decomposing it into physically distinct components. The measured distribution is separated into an ideal baseline defined by programming conditions, intrinsic broadening evaluated at the page-level, and interaction-induced contributions emerging at the block-level. Intrinsic variation is dominated by read variation including random telegraph noise (RTN), while initial $V_{\text{th }}$ shift (IVS) also contributes to distribution degradation. Among interaction effects, word-line (WL) coupling induces width broadening, whereas other mechanisms primarily cause $\boldsymbol{V}_{\text{th }}$ shift without distribution widening. This decomposition clarifies which degradation components are practically improvable and which are fundamentally constrained by device architecture and operation.

A novel vertical-nand (V-nand) flash memory architecture with an intercell charge trap layer (ICTL) is proposed to enhance the erase efficiency and data retention based on experimentally calibrated simulation results. The ICTL is an additional charge trap layer (CTL) located within the intercell region, physically separated from the main CTL. In this work, the ICTL is designed to store electrons for two purposes: 1) to boost the erase efficiency by increasing the barrier height against electron back-tunneling and 2)to improve the data retention by providing electrostatic stabilization of charge in the CTL. The proposed ICTL V-nand is evaluated using TCAD simulations calibrated to experimental data of conventional V-nand devices. In particular, the ICTL V-nand improves the erase efficiency by 25% and mitigates charge degradation due to lateral migration (LM) by 30% under the program-erase-program (PEP) pattern compared with the conventional structure. Therefore, the ICTL V-nand offers significant advantages in logical scaling, providing a wider memory window (MW), while lowering the required operating voltage and enhancing immunity to LM.

Novel charge-ring (CR) vertical NAND (CR-VNAND) flash memory is proposed to improve the retention characteristics under aggressive z-scaling conditions. By initially charging the hole within the CR layer, the lateral electric field in the charge trap layer (CTL) is effectively mitigated, thereby suppressing hole lateral migration (LM). Notably, the suppression of electron LM remains unaffected in CR-VNAND due to the deep electron trap energy level. Compared to conventional VNAND flash memory, the proposed CR-VNAND significantly enhances retention characteristics, improving V-th stability up to 42% and 35% in the erase-program-erase (EPE) pattern and program-erase-program (PEP) pattern, respectively. In particular, the retention advantage of CR-VNAND remains effective with aggressive z-scaling. In addition, a 17% enhancement in program efficiency enables a larger program window. These findings provide practical design insights for z-scaling in VNAND flash devices.

The introduction of 3D-VNAND structure has led to a significant increase in bit density, and the evolution to Cell Over Peripheral circuits (COP) has further accelerated this trend. However, the cell fabrication process following the peripheral transistor process can significantly impact the characteristics of peripheral transistors, posing a challenge in achieving high performance and reliability in VNAND flash memory devices. In this article, we present the index of Hydrogen-induced Boron penetration, so called HBp-index, a novel quantitative model that explains the combination effect of hydrogen and process heat on peripheral transistors in 3D NAND flash memory. We observed the index linearly matched with the change of the electrical characteristics of the transistors for various heat processes. Furthermore, it was found from the result that hydrogen induced by cell process caused degradation of HCI by 42mV and NBTI by 22mV, consistent with previous papers [5], [6].

We present a hydrogen-assisted enhanced boron diffusion model in oxide. By introducing the B+OH reaction and BOH diffusion, the model could reproduce the enhanced B diffusion in the presence of high concentrations of hydrogen, which has been reported by previous studies. The model was applied to predict the B profile in the p-type MOSFET and the resulting B profiles were used to predict the threshold voltage (Vth) and the short channel effects (SCE). The simulation results are in good agreement with the measurements. Therefore, the model would be beneficial to optimize the H-involved process conditions.

The continuous increase of total number of word-line (WL) layers and the reduction of unit cell size make it difficult to implement quad-level cell (QLC) in 3D-NAND flash. In this paper, we introduce several technological breakthroughs to realize QLC with high performance and reliability for $7^{\mathrm{th}}$ generation 3D-NAND (7 th QLC). By introducing advanced technologies, the QLC reliability is enhanced by 74% compared to before the improvement, which is equivalent the previous generation QLC 3D-NAND with 92-layer (5 th QLC). Furthermore, the average performance is 25% increased and bit density is doubled compare to $5^{\mathrm{th}}$ QLC.

The industry leading 8th generation 1Tb 3D-NAND flash memory (8th 3D-NAND) has been developed while possessing the smallest unit cell volume among all 3D-NAND products. Despite increasing stacking layers from 176 to 236, we improved the uniformity of channel hole size by utilizing the state of the art HARC (high-aspect ratio contact) etching technology. Degradation of interference and retention characteristics due to the cell scale-down is overcome by several ingenious technologies, leading to the development of highly reliable high performance device.

Over the past few decades, a greater need for 3D Vertical NAND (V-NAND) flash memory storage capacity has emerged. Compared to its prevailing technical predecessor, a quad-level cell (QLC) NAND flash memory can be a perfect replacement to meet the needs for the higher density and lower cost non-volatile memory market. However, despite these benefits, QLC’s market share has not been growing significantly because of its worse device reliability and slower performance. In this Paper, a new highly mass-producible and highly reliable 1Tb QLC 3D NAND flash memory with 176-word-line (WL) and Cell-Over-Peripheral (COP) architecture along with a number of significant process advancements will be presented.

We demonstrated that polycrystalline-Si (poly-Si) channel mobility could be significantly enhanced through a combined effect of grain size engineering and Ge diffusion into the poly-Si channel. By crystallizing an amorphous-Ge/Si stack via thermal annealing, grain size enlargement and Ge diffusion occur together, resulting in an increase of the channel mobility of up to lpzrptsim100%. The enhanced poly-Si channel mobility improved the program and erase speeds by 55.8% and 30.5%, respectively, with no adverse effect on retention and endurance characteristics.

We demonstrated that channel mobility and cell current could be increased through Ge diffusion engineering and H 2 plasma treatment in a poly-Si channel. Even though the Ge channel has a higher intrinsic mobility than the Si channel, a typical poly-SiGe channel has inferior channel characteristics due to high interface trap density (D it ) and bulk trap density caused by Ge. We propose a novel technique to control the Ge profile along the depth direction of the channel to realize lower Ge concentration at the gate dielectric interface and higher Ge concentration at the channel bulk. This Ge profile could achieve reduced D it and enhanced channel mobility. Furthermore, the bulk traps caused by Ge are effectively reduced by H 2 plasma treatment. These techniques increased the channel mobility to 32%, which can help increase the channel mobility of devices where poly-Si channels are used.

Grain boundary (GB) is a significant factor that deteriorates the transfer characteristics of poly-Si thin-film transistors (TFTs). In this study, we utilized the synergistic effect of microwave annealing (MWA) and high-pressure hydrogen annealing (HPHA) to effectively reduce grain boundary trap (GBT) density, resulting in improved field-effect mobility (μ) and subthreshold swing (SS). To investigate the synergistic effect of MWA and HPHA, the transfer characteristics of rapid thermal annealing and forming gas annealing devices were compared and analyzed as control devices. Furthermore, the mechanism of SS and mobility enhancement can be quantitatively understood by lowering the GB barrier height. In addition, Raman spectroscopy proved that poly-Si crystallinity was improved during MWA. Our results showed that MWA and HPHA play a vital role in reducing GBT density and improving poly-Si TFT characteristics.

A novel 3D NAND Flash memory device with 17X WL (Word line) layers has been successfully developed. COP(Cell Over Peripheral) Structure has been applied, improving tR and tPROG by 11% and 20%, respectively. Compared with our previous product(6th generation), the bit density is increased by 70% through cell volume scaling and COP structure. Several breakthrough processes have been successfully combined to achieve this new structure. Double stack process, low stress W(tungsten), MSE(Multi Step Etch), and channel hole side-wall butting etc. In addition, the double stack process was applied to significantly improve the channel hole profile. As a result, better cell operation characteristics were achieved.

An industry leading 128-layer single-stack 3D-NAND Flash memory with high reliability cell characteristics is successfully developed for the first time. Single-stack etching of 128 layers brings about various deformation of hole profile, which leads to the degradation of cell characteristics. The degradation of cell characteristics has been overcome by advanced HARC (high-aspect ratio contact) etching process and ONO material engineering. The single-stack NAND Flash memory still has a potential to be developed further with the advanced single-stack technology.

Architecture change from BCS (Body Contact Spacer) scheme to CSOB (Channel-hole Sidewall ONO Butting) scheme for the 7th-generation 3D-NAND flash memory is discussed, which has been driven to adopt COP (Cell Over Peripheral circuits) scheme. Device considerations, such as cell-to-cell interference, cell current, and charge loss in the 7th-generation 3D-NAND are reviewed and solutions are suggested that lead to the world smallest unit cell volume in flash memory.

We demonstrate for the first time that the use of an anti-ferroelectric film for the blocking layer of a charge trap flash (CTF) device significantly improves memory performance. The CTF device with the anti-ferroelectric blocking layer shows a larger program window and a faster program/erase speed without degradation of the retention and endurance characteristics, compared to the conventional CTF device with a typical high-k dielectric blocking layer. It is found that a capacitance boosting effect by the anti-ferroelectric layer is the origin of the performance enhancement.

Scaling limitations in planar-NAND cell are discussed, including the depletion of floating gate and anomalous programming behavior. It is inevitable to have a paradigm shift to 3D-NAND due to numerous scaling limitations of planar NAND. However, the process complexity also increases in 3D-NAND as the mold height goes up in an exponential trend. Thus, scaling down of mold pitch is required, which degrades the cell characteristics. COP (Cell over Peripheral) 3D-NAND architecture has been developed as an area-scaling technology. CSL (Common-Source Line) junction leakage and p + junction leakage at peripheral transistors have been improved by increasing the grain size and the thickness of barrier metal, respectively.