This paper empirically analyzes how universities decide which courses to offer and the implications of these decisions for students. At a sample university, course offerings significantly impact student course choices and implicitly sacrifice student utility to increase enrollment in STEM and business and occupational courses. This is because new course sections in these fields have slightly smaller effects on student utility and cost substantially more than new offerings in other fields. The university changes its course offerings in counterfactual scenarios, and ignoring these responses leads to understating the effects of interventions.

We show that stricter grading policies in STEM courses reduce STEM enrollment, especially for women. We estimate a model of student demand for courses and optimal effort choices given professor grading policies. Grading policies are treated as equilibrium objects that in part depend on student demand for courses. Differences in demand for STEM and non‐STEM courses explain much of why STEM classes give lower grades. Restrictions on grading policies that equalize average grades across classes reduce the STEM gender gap and increase overall enrollment in STEM classes.

Amber is a system-on-chip (SoC) with a coarse-grained reconfigurable array (CGRA) for acceleration of dense linear algebra applications, such as machine learning (ML), image processing, and computer vision. It is designed using an agile accelerator–compiler codesign flow; the compiler updates automatically with hardware changes, enabling continuous application-level evaluation of the hardware–software system. To increase hardware utilization and minimize reconfigurability overhead, Amber features the following: 1) dynamic partial reconfiguration (DPR) of the CGRA for higher resource utilization by allowing fast switching between applications and partitioning resources between simultaneous applications; 2) streaming memory controllers supporting affine access patterns for efficient mapping of dense linear algebra; and 3) low-overhead transcendental and complex arithmetic operations. The physical design of Amber features a unique clock distribution method and timing methodology to efficiently layout its hierarchical and tile-based design. Amber achieves a peak energy efficiency of 538 INT16 GOPS/W and 483 BFloat16 GFLOPS/W. Compared with a CPU, a GPU, and a field-programmable gate array (FPGA), Amber has up to 3902 $\times$ , 152 $\times$ , and 107 $\times$ better energy-delay product (EDP), respectively.

We investigate how improving the signal quality of grades could enhance the matching of students to selective opportunities that are awarded early in academic programs. To do so, we develop methods to measure the signal quality of grades and to estimate the impact of changes to university policies on the identification of exceptional students for these opportunities. We focus on law schools, a setting where students are awarded important academic and professional opportunities after just one year of a three-year program. Using transcript data from a top law school over a 40-year period, we document large gains in identifying exceptional students if changes were made to certain personnel, course, and grading policies. Our findings provide motivation and a blueprint for how universities could leverage their internal records to ensure that fewer exceptional students miss out on selective opportunities.

With the slowing of Moore’s law, computer architects have turned to domain-specific hardware specialization to continue improving the performance and efficiency of computing systems. However, specialization typically entails significant modifications to the software stack to properly leverage the updated hardware. The lack of a structured approach for updating the compiler and the accelerator in tandem has impeded many attempts to systematize this procedure. We propose a new approach to enable flexible and evolvable domain-specific hardware specialization based on coarse-grained reconfigurable arrays (CGRAs). Our agile methodology employs a combination of new programming languages and formal methods to automatically generate the accelerator hardware and its compiler from a single source of truth. This enables the creation of design-space exploration frameworks that automatically generate accelerator architectures that approach the efficiencies of hand-designed accelerators, with a significantly lower design effort for both hardware and compiler generation. Our current system accelerates dense linear algebra applications but is modular and can be extended to support other domains. Our methodology has the potential to significantly improve the productivity of hardware-software engineering teams and enable quicker customization and deployment of complex accelerator-rich computing systems.

Dedicated hardware accelerators popular for imaging, vision, and machine learning (ML) applications

Achieving high code reuse in physical design flows is challenging but increasingly necessary to build complex systems. Unfortunately, existing approaches based on parameterized Tcl generators support very limited reuse as designers customize flows for specific designs and technologies, preventing their reuse in future flows. We present a vision and framework based on modular flow generators that encapsulates coarse-grained and fine-grained reusable code in modular nodes and assembles them into complete flows. The key feature is a flow consistency and instrumentation layer embedded in Python, which supports mechanisms for rapid and early feedback on inconsistent composition. We evaluate the design flows of successive generations of silicon prototypes built in TSMC16, TSMC28, TSMC40, SKY130, and IBM180 technologies, showing how our approach can enable significant code reuse in future flows.

Amber is a system-on-chip (SoC) with a coarse-grained reconfigurable array (CGRA) for acceleration of dense linear algebra applications such as machine learning (ML), image processing, and computer vision. It achieves a peak energy efficiency of 538.0 INT16 GOPS/W and 483.3 BFloat16 GFLOPS/W. We maximize CGRA utilization and minimize reconfigurability overhead through (1) dynamic partial reconfiguration of the CGRA that enables higher resource utilization by allowing multiple applications to run at once, (2) efficient streaming memory controllers supporting affine access patterns, and (3) low-overhead transcendental and complex arithmetic operations. Compared to a CPU, a GPU, and an FPGA, Amber achieves up to 3902x, 152x, and 88x better energy-delay product (EDP).

Achieving high code reuse in physical design flows is challenging but increasingly necessary to build complex systems. Unfortunately, existing approaches based on parameterized Tcl generators support very limited reuse as designers customize flows for specific designs and technologies, preventing their reuse in future flows. We present a vision and framework based on modular flow generators that encapsulates coarse-grained and fine-grained reusable code in modular nodes and assembles them into complete flows. The key feature is a flow consistency and instrumentation layer embedded in Python, which supports mechanisms for rapid and early feedback on inconsistent composition. We evaluate the design flows of successive generations of silicon prototypes built in TSMC16, TSMC28, TSMC40, SKY130, and IBM180 technologies, showing how our approach can enable significant code reuse in future flows.

The emergence of immunomodulators as effective cancer treatments has been an important advance in cancer therapy. The combination therapy of BRAF/MEK inhibition with or without anti-CTLA-4 treatment causes an immunostimulatory effect that has greatly reduced death from melanoma. In this article, we present the case of a patient with prior multiple sclerosis (MS) and who later developed metastatic malignant melanoma, had a marked increase of magnetic resonance imaging (MRI) findings after treatment with the combination of trametinib (MEK) and dabrafenib (BRAF), diagnostic question of metastatic disease versus new MS lesions without brain biopsy is discussed. A healthy 49-year-old man was diagnosed with MS in October 2012. He was stable with an oral disease modifying drug until March of 2016 when the patient discovered a lump in his right groin. Biopsy was positive for S100 and BRAF V600 mutation. Combination MEK/BRAF was given and after immunotherapy an MRI showed 25 new gadolinium-enhancing lesions thought to be metastases. A brain biopsy was recommended but neurology and neuroimaging consultation showed that the MRI was consistent with demyelination (oval/ovoid, homogeneous and open-ring enhancement, and predominance of the central vein sign within lesions) rather than metastasis. Treatment for MS has been successful and there has been no return of his melanoma in 4 years. New immunotherapies are lifesaving but the modulation of the immune system can cause unpredictable events such are markedly increased MS activity. The awareness of the diagnostic value of the central vein sign provided a better outcome for this patient and could be a model in the future for others.

Achieving high code reuse in physical design flows is challenging but increasingly necessary to build complex systems. Unfortunately, existing approaches based on parameterized Tcl generators support very limited reuse and struggle to preserve reusable code as designers customize flows for specific designs and technologies. We present a vision and framework based on modular flow generators that encapsulates coarse-grain and fine-grain reusable code in modular nodes and assembles them into complete flows. The key feature is a flow consistency and instrumentation layer embedded in Python, which supports mechanisms for rapid and early feedback on inconsistent composition. The approach gradually types the Tcl language and allows both automatic and user-annotated static assertion checks. We evaluate the design flows of successive generations of silicon prototypes designed in TSMC16, TSMC28, TSMC40, SKY130, and IBM180 technologies, showing how our approach can enable significant code reuse in future flows.

Compilation times for large Xilinx devices, such as the Amazon F1 instance, are on the order of several hours. However, today's data center designs often have many identical processing units (PUs), meaning that conventional design flows waste time placing and routing the same problem many times. Furthermore, the connectivity infrastructure of a design tends to be finalized before the PUs, resulting in unnecessary recompilation of a large fraction of the design. We present an open source flow where the connectivity infrastructure logic is implemented ahead of time and routed to many interface blocks that border available slots for PUs. As architects iterate on their PU designs, they only need to perform a single set of parallel, independent compile runs to implement and route the PU alongside each distinct interface block. Our RapidWright-based system stitches the implemented PU into the available slots in the connectivity logic, requiring no additional routing to finalize the design. Our system is able to generate working designs for Amazon F1, and reduces compilation time over the standard monolithic compilation flow by an order of magnitude for designs with up to 180 PUs. Our experiments also show that there is future potential for an additional 4X runtime improvement when relying on emerging open source place and route tools.

Although an agile approach is standard for software design, how to properly adapt this method to hardware is still an open question. This work addresses this question while building a system on chip (SoC) with specialized accelerators. Rather than using a traditional waterfall design flow, which starts by studying the application to be accelerated, we begin by constructing a complete flow from an application expressed in a high-level domain-specific language (DSL), in our case Halide, to a generic coarse-grained reconfigurable array (CGRA). As our under-standing of the application grows, the CGRA design evolves, and we have developed a suite of tools that tune application code, the compiler, and the CGRA to increase the efficiency of the resulting implementation. To meet our continued need to update parts of the system while maintaining the end-to-end flow, we have created DSL-based hardware generators that not only provide the Verilog needed for the implementation of the CGRA, but also create the collateral that the compiler/mapper/place and route system needs to configure its operation. This work provides a systematic approach for desiging and evolving high-performance and energy-efficient hardware-software systems for any application domain.

We present Fleet, a framework that offers a massively parallel streaming model for FPGAs and is effective in a number of domains well-suited for FPGA acceleration, including parsing, compression, and machine learning. Fleet requires the user to specify RTL for a processing unit that serially processes every input token in a stream, a far simpler task than writing a parallel processing unit. It then takes the user's processing unit and generates a hardware design with many copies of the unit as well as memory controllers to feed the units with separate streams and drain their outputs. Fleet includes a Chisel-based processing unit language. The language maintains Chisel's low-level performance control while adding a few productivity features, including automatic handling of ready-valid signaling and a native and automatically pipelined BRAM type. We evaluate Fleet on six different applications, including JSON parsing and integer compression, fitting hundreds of Fleet processing units on the Amazon F1 FPGA and outperforming CPU implementations by over 400x and GPU implementations by over 9x in performance per watt while requiring a similar number of lines of code.

Existing deep neural network (DNN) frameworks optimize the computation graph of a DNN by applying graph transformations manually designed by human experts. This approach misses possible graph optimizations and is difficult to scale, as new DNN operators are introduced on a regular basis. We propose TASO, the first DNN computation graph optimizer that automatically generates graph substitutions. TASO takes as input a list of operator specifications and generates candidate substitutions using the given operators as basic building blocks. All generated substitutions are formally verified against the operator specifications using an automated theorem prover. To optimize a given DNN computation graph, TASO performs a cost-based backtracking search, applying the substitutions to find an optimized graph, which can be directly used by existing DNN frameworks. Our evaluation on five real-world DNN architectures shows that TASO outperforms existing DNN frameworks by up to 2.8X, while requiring significantly less human effort. For example, TensorFlow currently contains approximately 53,000 lines of manual optimization rules, while the operator specifications needed by TASO are only 1,400 lines of code.

Summary I use transcript data from Duke University and a correlated learning model to measure the signal quality of grades across academic fields. I find science, engineering, and economics grades are significantly more informative than humanities and social science grades. The correlated learning structure allows grades in one field to signal abilities in all fields. This sometimes generates information spillovers so powerful that science, engineering, and economics grades inform humanities and social science beliefs more than humanities and social science grades. I show that grade compression reduces signal quality but cannot explain the differences in signal quality across academic fields.

Modern analytics applications use a diverse mix of libraries and functions. Unfortunately, there is no optimization across these libraries, resulting in performance penalties as high as an order of magnitude in many applications. To address this problem, we proposed Weld, a common runtime for existing data analytics libraries that performs key physical optimizations such as pipelining under existing, imperative library APIs. In this work, we further develop the Weld vision by designing an automatic adaptive optimizer for Weld applications, and evaluating its impact on realistic data science workloads. Our optimizer eliminates multiple forms of overhead that arise when composing imperative libraries like Pandas and NumPy, and uses lightweight measurements to make data-dependent decisions at run-time in ad-hoc workloads where no statistics are available, with sub-second overhead. We also evaluate which optimizations have the largest impact in practice and whether Weld can be integrated into libraries incrementally. Our results are promising: using our optimizer, Weld accelerates data science workloads by up to 23X on one thread and 80X on eight threads, and its adaptive optimizations provide up to a 3.75X speedup over rule-based optimization. Moreover, Weld provides benefits if even just 4--5 operators in a library are ported to use it. Our results show that common runtime designs like Weld may be a viable approach to accelerate analytics.

From the inception of the integration of predominantly White institutions in higher education marked by Sweatt v. Painter in 1950, The University of Texas at Austin (UT Austin) has been a battleground for educational equity. The university continues to find itself at ground zero in the battle for race and equity in higher education and embroiled in the debate over affirmative action, first in Hopwood v. Texas (1996) and then in Fisher v. University of Texas at Austin (2013; 2016). For these reasons, UT Austin serves as a bellwether institution for public, predominantly White institutions (PWIs) when it comes to integration. The legal challenges, coupled with evidence of a challenging campus climate for students of color, reflect the kind of hostility recently reported at Michigan, UCLA, and other public flagship institutions such as Texas AM Fries-Britt, Identifying; Griffin). This study documents the experiences of the first Black graduates of the prestigious Plan II honors degree program who attended UT Austin in the late 1970s and early 1980s. While participants lauded the rigor, breadth, and small size of the honors program, they also experienced many of the same struggles as present-day Black students, including tokenism, racism, pressure to prove their worth, and a desire for kinship. These findings can help to improve honors programs by illuminating the unique challenges experienced by Black honors students of the past and making connections to higher education today. STUDY BACKGROUND The Plan II Honors Program was founded in 1935 by H. T. Parlin, Professor of English and Dean of the College of Arts and Sciences (Click). Since then, the program has become one of the university's and the nation's premier honors programs (Sullivan; Willingham). Plan II alumni are among the most heralded graduates of UT Austin, with the list of prominent Plan II alumni including former U.S. Attorney General Ramsey Clark, Dr. Betty Sue Flowers, Kinky Friedman, and Austin Ligon (founder of CarMax) (McAndrew). While these alumni are worthy of recognition, they are all White. Black Plan II alumni of note include filmmaker Shola Lynch and former Texas State Representative Ron Wilson (Plan II Honors), but Black students are under-represented in the Plan II student body. Two factors that account for the underrepresentation are a separate Plan II application, in addition to the one required of all UT Austin students, and the fact that high-achieving students of color who apply to elite institutions often receive multiple competitive scholarship offers. These factors contribute to UT Austin's loss of prospective Black students to other universities, especially elite private institutions. This moment in U.S. history is an opportune time to examine the involvement and experiences of Black students at UT Austin, both in Plan II Honors and beyond. In 2010, the documentary film When I Rise was released, reflecting on the life of opera superstar Barbara Smith Conrad, who was in the first class of Black undergraduate students to enter UT Austin in 1956 (Hames). …