Anyone who has spent any time with Mark knows that he loves puzzles. His office at Stanford is full of puzzles: some he built himself, some crafted from beautiful hardwood, and some simple children's toys. Each of them has their own aesthetic and their unique attraction to Mark. So, in many ways, it's no surprise that what attracted him to cofounding Rambus back in 1990 was a puzzle posed by Rambus cofounder Mike Farmwald: could they, using circuit and architecture techniques, increase the bandwidth of the dynamic random access memory (DRAM) interface tenfold without changing process technology?

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UIp-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10(-9). The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm(2) per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.