A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The. clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PILL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies.

A 10 Gb/s CDR in SiGe BiCMOS technology featuring multistandard compliance with SDH/SONET and 10 Gb Ethernet specs and generated jitter below 65 mUlpp is presented. The CDR features a 20 mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize CPM and a dual loop PLL architecture with external reference clock and a novel PD topology. Power consumption is below 780 mW from 2.5 and 3.3 V supplies.