High-fidelity coherent population transfer plays a vital role in the realization of quantum memories. However, population transfer with high performance across a broad frequency range is still challenging due to the finite Rabi coupling strength limited by laser powers. Here we propose a population-transfer scheme by suturing adiabatic control pulses where each pulse covers a certain frequency interval and that are connected in a way that neighboring adiabatic pulses have opposite chirping directions. Taking the widely used hyperbolic-square-hyperbolic pulse as an example, we demonstrate that rapid and robust population transfer can be achieved. The transfer bandwidth scales linearly with the number of suture pulses while maintaining high fidelity, even at the suture points where adiabaticity breaks down. Crucially, these pulses can be realized by a single laser by means of temporal multiplexing. For a given bandwidth, this strategy substantially reduces the operational time, which is necessary for on-demand read out and suppression of decoherence effects. Our scheme enables a dramatic increase in multimode storage capacity, and paves the way for realizing practical quantum networks.

Infrared astronomical equipment is pivotal in advancing our understanding of the universe, particularly through ground-based observations, which remain the primary mode of astronomical study. In this paper, we introduce the development and performance characterization of an H-band Mercury Cadmium Telluride (MCT) infrared camera designed for astronomical observations. We computed the photon transfer curve (PTC) for each pixel and fitted these curves to derive pixel-level gain. The results reveal a spatial non-uniformity of detector pixel-level gain, which correlates with changes in field of view (FOV). By employing FOV compensation, we achieved more uniform gain distribution. This testing approach allows for a more accurate performance evaluation of scientific-grade astronomical cameras, providing a robust foundation for subsequent astronomical image analysis and benefiting the field of infrared astronomy.

In clock distribution and synchronization systems with automatic phase compensation, the high-precision phase shifter is a critical component. This paper presents a coarse-fine architecture phase shifter capable of wide-range phase shifting with a sub-10 ps resolution. The proposed circuit employs a Delay-Locked Loop (DLL) to implement coarse phase adjustment, complemented by a Digital-to-Time Converter (DTC) with closed-loop feedback for fine phase adjustment. A prototype Application-Specific Integrated Circuit (ASIC) was designed and fabricated using a 180 nm CMOS process, and a clock synchronization verification system was also constructed to evaluate the ASIC's performance. Test results demonstrate that the ASIC achieves clock phase shifting with an average step size of approximately 8 ps and a dynamic range of 8 ns. Furthermore, the ASIC exhibits a latency variation of less than 20 ps across multiple power cycles. In addition, clock synchronization accuracy was measured to be better than 10 ps peak-to-peak, when the optical fiber was placed in a climate chamber with the temperature variation of up to 20 degrees C.

In infrared imaging, pixel non-uniformity due to manufacturing and technological limitations significantly degrades image quality, posing a critical challenge for high-performance applications. This issue is especially pronounced in the field of infrared astronomical observation, where the scientific integrity of the data must be ensured when correcting infrared images. In addition, the coupling capacitance between pixels leads to nonlinear effects in pixel sensitivity. To address these challenges, a non-uniformity correction (NUC) algorithm was introduced that utilizes classification and regression tree segmentation. This approach enables precise corrections by adapting to varying illuminance levels, a capability not fully explored in existing solutions. In our method, we innovatively segment the pixel response curves into distinct low and high illuminance ranges and apply customized corrections for each segment to enhance the accuracy of correction. Evaluations using real image data demonstrate that our method enhances image quality and consistency. (c) 2025 Society of Photo-Optical Instrumentation Engineers (SPIE)

High-speed serial link transmitters have been widely integrated in front-end application specified integrated circuits (ASICs). However, it is difficult to achieve high data bandwidth, low power consumption, and low jitter at the same time. In this article, a 4x6.25-Gb/sserial link transmitter core has been designed for high-speed front-end ASICs. The transmitter core is implemented in a commercial 0.18- $\mu $ m CMOS technology. The core consists of a common ring-oscillator-based phase-locked loop (PLL) and four individual transmitter channels. Each channel contains a two-stage 20:2 serializer, a two-tap half-rate feed-forward equalizer (FFE), and a clock manager circuit. With a new architecture of the final-stage serializer and half-rate FFE and an optimized selection scheme of the flip-flops in the serializer, the number of current mode logic (CML) devices is decreased and the total power consumption is significantly reduced compared with previous works, while maintaining high data bandwidth and low jitter. To validate the designed transmitter core, a prototype chip has been fabricated and tested. The test results show that the transmitter core operates from 3.5 to 6.75 Gb/s. At a data rate of 6.25 Gb/s, the PLL outputs a 3.125-GHz clock, with a phase jitter of 1.006-ps rms, and the total jitter (Tj) of the output data is 45.5 ps at a bit error rate (BER) of 1x10(-12) . The core occupies an area of 0.44 mm2 and consumes 27.8 mW/Gb/s at a 1.8-V supply.

In the field of quantum optics, especially in various experiments involving characterizing entangled photon pairs or quantum correlation effects, coincidence systems are primarily employed to detect and record temporal correlations between multiple photon events. Certain experiments propose higher requirements for the time precision of coincidence electronics, aiming to achieve high-precision time measurements with single-channel time resolution of ~10 ps RMS. To support diverse quantum optics experiments, a 32-channel high-precision coincidence module has been designed and fabricated. A series of tests have been conducted, and the results show that the time precision of each channel of the electronics is better than 10 ps RMS. Furthermore, preliminary experimental applications in quantum optics experiments have been successfully conducted.

This article presents the design of a sub-10-ps resolution 16-channel time-to-digital converter (TDC) for high-energy physics applications. The architecture is based on a coarse counter and a two-stage interpolator. Dual 12-bit gray counters are employed to record the timestamp for coarse conversion extending the measurement dynamic range, while the interpolator is designed with a coarse-fine structure for fine conversion. The first interpolation stage is implemented with a multiphase delay line with a resolution of 89 ps, while the second interpolation stage is achieved with a Vernier delay line with a subgate-delay resolution of 7 ps. A low-jitter compact multiplying delay-locked loop (MDLL) generates an 800-MHz internal clock signal out of 50-MHz external reference clock, which shrinks the number of delay elements to cover one period of the coarse clock. Operation at higher frequency also provides high throughput and short conversion time. A new differential delay cell and a phase detector composed of phase-frequency detector and bang-bang phase detector (BBPD) are proposed in the delay-locked loop (DLL) design to reduce the nonlinearity. The TDC offers a measurement range of 5.12 mu s and 7-ps resolution. Fabricated in a 1.8-V 180-nm CMOS process, the chip occupies a die size of 2.2x2.2 mm. The measured single-shot precision (SSP) is better than 7.5 ps, while the total static power consumption is 140 mW for 16 channels and the dynamic power consumption is approximately 6.5 mW/MHz/channel.

Micro-Pattern Gas Detectors (MPGDs) have become an important component in high-energy physics experiments due to their good spatial and time resolution. This paper presents the design and testing of a 512-channel front-end electronics (FEE) prototype based on a 32-channel custom application-specific integrated circuit (ASIC) to read the Ring Imaging Cherenkov (RICH) detector. The test results show a gain non-uniformity of below 5% and a charge resolution of better than 0.24 fC, meeting the design requirements. The time resolution is around 1 ns root mean square (RMS). The readout electronics have also been validated with the prototype RICH detector, in the Super Tau-Charm Facility (STCF), and clear hit images can be measured with the ^55Fe radiation source.

The Super τ -Charm Facility (STCF) is a high-luminosity electron-positron collider under development in China. STCF requires excellent particle identification for charged hadrons within its energy range, necessitating a ≥4σ separation for π /K identification at the momentum range of 2 GeV/c and below. To meet these stringent requirements, a Cherenkov detector, Ring Imaging Cherenkov counter(RICH), has been selected as the baseline candidate for STCF. Our research focuses on a cascaded micro-pattern gaseous detector based on THGEM and Micromegas, providing high gain, large area coverage, and high counting rate capability. Furthermore, we are exploring the feasibility of a novel photodetector based on a double micro-mesh gaseous structure.

High-speed serial link transmitters have been widely integrated in front-end ASICs. However, it’s difficult to achieve high data bandwidth, low power consumption and low jitter at the same time. In this paper, a 4×6.25 Gbps serial link transmitter core has been designed for high-speed front-end ASICs. The transmitter core is implemented in a commercial 0.18-μm CMOS technology. The core consists of a common ring-oscillator based PLL and four individual transmitter channels. Each channel contains a two-stage 20:2 serializer, a two-tap half-rate feed-forward equalizer and a clock manager circuit. With a new architecture of the final-stage serializer and half-rate feed forward equalizer, and an optimized selection scheme of the flip-flops in the serializer, the number of CML devices is decreased and the total power consumption is significantly reduced compared with previous works, while maintaining high data bandwidth and low jitter. To validate the designed transmitter core, a prototype chip has been fabricated and tested. The Test results show that the transmitter core operates from 3.5 to 6.75 Gbps. At a data rate of 6.25 Gbps, the PLL outputs a 3.125 GHz clock, with a phase jitter of 1.006 ps RMS, and the total jitter of the output data is 45.5 ps at a bit error rate of 1×10 -12 . The core occupies an area of 0.44 mm 2 and consumes 27.8 mW/Gbps at a 1.8 V supply.

In this paper, we design a simulation test system to test the readout and drive circuit of the Front-End electronics board (FEB) of the CCD detector system of Wide Field Survey Telescope (WFST). For fast and accurate testing, the CCD simulation test system can c 20-channel clock detection, 16-channel bias, and 16-channel bias noise detection. In addition, the simulation test system can also provide two channels of analog CCD waveform output for testing FEB waveform sampling circuits. The analog CCD waveform output module consists of a digital waveform output module and an analog waveform output module, which can be selected according to specific requirements. The simulation test system has been used to test the FEB performance of the Wide Field Survey Telescope.

The time-interleaved analog-to-digital conversion (TIADC) technique provides an effective way to achieve high sampling speed. However, a critical challenge in TIADC design arises from the presence of mismatches among parallel sub-analog-to-digital converters (ADCs), which detrimentally affect system performance. In this article, we propose a machine-learning-based method to address these mismatches across a broadband of input signal frequencies. Different from conventional approaches, this method avoids complex and specific matrix operations and reduces the compensation filter order required to achieve a given reconstruction accuracy. To assess the efficacy of our proposed method, we designed a 5-Gs/s 12-bit TIADC system. Through extensive testing, the results demonstrate notable improvements in the effective number of bits (ENOBs) following real-time calibration. Specifically, for input frequencies below 500 MHz, the ENOB surpasses 9 bits, while for frequencies ranging from 500 MHz to 1.25 GHz, it exceeds 8 bits.

Drift chambers are essential in high-energy collider experiments for tracking the trajectory of charged particles. With the increase in peak luminosity, the detector's counting rate also rises, leading to challenges such as high beam backgrounds and an increased probability of signal pile-up in a single drift chamber channel. The Super Tau-Charm Facility (STCF) is a new electron-positron collider proposed by the Chinese particle physics community and the Main Drift Chamber (MDC) is the primary component of the STCF tracking system. The average hit rate of the innermost layer is 440 kHz with the cell size of 1 cm. This high count rate increases the pile-up probability of waveforms, making it difficult to achieve waveform discrimination even with optimized readout electronics performance. Modifying the cell size from approximately 1 cm to 5 mm is expected to decrease the innermost layer hit rate to approximately 210 kHz per channel. This paper presents a novel algorithm for waveform distinction using digital waveform data and integration curves. The algorithm is implemented on an evaluation board based on the Xilinx FPGA to achieve real-time waveform distinction. The algorithm's performance is validated through testing with the evaluation board. The test results indicate that the probability of distinction closely matches the theoretical value, the efficiency of the algorithm is about 96%, and the error probability is less than 4%. This result can serve as a reference for optimizing the MDC structure.

Waveform digitization at sampling rates up to several giga-samples per second is one of the approaches to achieve high-precision time measurements. In recent years, achieving high precision at lower sampling rates has emerged as a significant research topic. In this article, we focus on time measurement electronics, in which the bandpass sampling method is applied to obtain high precision at a sampling rate of roughly 100 MSps. An analog front-end circuit is designed, in which the input pulse signal is bandpass-filtered and amplified before sampling. A pipelined real-time time extraction algorithm is designed using the techniques of interpolation and cross correlation. A 1024-point fast Fourier transform algorithm is adopted to implement the cross correlation operation. Four time measurement channels are implemented in a mid-range field-programmable gate array, and the measurement rate of 116 kHz is achieved. Tests are conducted to evaluate the performance of the timing system. The typical RMS precision is better than 0.4 ps.

To enhance signal generation capabilities, improve the performance of experimental and testing equipment, and promote innovation in related technological fields, this study aims to develop a high-bandwidth Arbitrary Waveform Generator (AWG) using the high-speed Digital-to-Analog Converter (DAC) ADA14S8000 made in China. The AWG uses the Direct Digital Waveform Synthesis (DDWS) principle with FPGA assistance to generate the waveform and achieved a storage depth of 2 Gpts with four Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM). The AWG comprises the waveform generation module, waveform conditioning module, and an operational software called AWGOperator. To initiate waveform generation, the AWGOperator is used to configure the waveform parameters, after which the waveform data are transferred to the waveform generation module via USB 3.0. Subsequently, the waveform generation module processes the data and generates the corresponding analogue waveform. Real-time adjustments of amplitude, bias, and delay parameters of the output waveform are also supported. The AWG provides a maximum sampling rate of 4 GSPS, a resolution of 14 bits, and a bandwidth specification of 1.6 GHz, and typical non-harmonic distortion of − 55 dBc and a phase noise of less than − 110 dBc/Hz at 10 kHz offset.

The peak luminosity of the Super Tau-Charm Facility (STCF) proposed by the Chinese particle physics community is about an order of magnitude greater than the present Tau-Charm factory. In the STCF, the MicroPattern Gas Detector (MPGD)-based Ring Imaging CHerenkov (RICH) detector used for Particle IDentification (PID) demands a new high integration, low dead time, and high-performance Application Specific Integrated Circuit (ASIC). In this paper, the design and testing of a 32-channel mixed-signal readout ASIC prototype is presented. Each channel consists of a Charge Sensitive Amplifier (CSA) based analog signal processing circuit, a valid signal discriminator, a Switched Capacitor Array (SCA), a 10-bit Wilkinson ADC, and a digital core. The ASIC provides charge measurement ranges from 48 fC to 10 pC with automatic calibration, five programmable peaking times from 70 ns to 1 μs, and can be operated at a sampling frequency of up to 240 MHz. The ASIC has been fabricated in a 0.18 μm CMOS technology and all the test results meet the requirements. In the case of an input capacitance of 20 pF and a charge collection time of 100 ns, the charge resolution of the full-scale signal is better than 0.38% and the time resolution of the 1/3-scale signals is better than 0.78 ns for all charge measurement range options, while the power consumption is less than 20 mW per channel. In particular, the Equivalent Noise Charge (ENC) is 627 e + 18.8 e/pF for the 48 fC charge measurement range. Besides, the maximum repetition event rate capability per channel is up to 125 kHz.

飞行时间（Time-Of-Flight, TOF）探测器是核与粒子物理实验的重要组成部分，多气隙电阻板室（Multi-gap Resistive Plate Chamber, MRPC）以其高时间精度的特点在TOF测量系统中被广泛应用，放大甄别结合时间数字变换是MRPC电子学读出的一种主流方案。为了满足MRPC读出电子学高时间精度、低功耗、高集成度的需求，设计了一款高速放大甄别原型芯片，该芯片集成了8个通道，通道内包含前置放大器、甄别器和输出驱动电路。前置放大器采用共栅极结构，这种低输入阻抗的结构有利于进行阻抗匹配设计；甄别器采用多级放大器级联的结构产生足够的增益，通过对信号进行饱和放大实现甄别功能；经过甄别后的脉冲波形信号由LVDS输出驱动器送到片外，其前沿和脉宽分别可以表征MRPC信号的到达时间和电荷量信息。基于180 nm的 CMOS 工艺完成了电路的设计、仿真和流片，并在实验室环境下完成了电子学性能测试。测试结果表明，在100 fC ~ 2 pC电荷量下，该芯片的时间精度好于10 ps (rms)，单通道功耗约为24 mW。

In this article, a prototype application-specific integrated circuit (ASIC) for the multipurpose time projection chambers (MTPCs) at back-streaming white neutron source is presented. The ASIC integrates 16 readout channels and is fabricated in a 0.18- $\mu \text{m}$ CMOS process. Each channel consists of a charge sensitive amplifier (CSA), a pole-zero cancellation (PZC), two bridged-T shapers, a baseline holder, and a fully differential output buffer. It provides the selectable charge ranges of 2 and 10 pC, the programmable peaking times from 110 ns to $1 \mu \text{s}$ , and an adjustable output common-mode voltage from 0.7 to 1.25 V. The ASIC has already been tested, and all the results meet the requirements. In the case of 100-pF input capacitance, 2-pC charge range, and 1- $\mu \text{s}$ peaking time, it features a maximum integral nonlinearity (INL) of 0.48% and an equivalent noise charge (ENC) of 0.749 fC, which makes the signal-to-noise ratio (SNR) at full-scale input over 2600. In particular, a crosstalk rejection ratio of 63 dB is obtained in this prototype ASIC using the baseline holder circuit in each channel to generate references for single-ended to differential conversion and isolate noise as well as crosstalk from the reference path.

The ring imaging Cherenkov(RICH)detector for particle identification(PID)is being evaluated for the future super tau-charm facility(STCF)complex.In this work,the prototype readout electronics for the RICH PID detector is designed.The prototype RICH PID detector is based on a thick gas electron multiplier combined with a micromegas detector for Cherenkov light detection.Con-sidering that there will be a large number(～690,000)of detector channels in future RICH detector,the readout electronics faces many challenges to precisely measuring time and charge information,such as reducing the noise,increasing density,and improving precision.The require-ments of the readout electronics are explored,the down-selection of the ASICs is made and thus a prototype readout electronics is designed and implemented.Tests are also conducted to evaluate the performance of the proto-type readout electronics,and the results indicate that the time resolution is better than～1 ns(RMS)when the input charge is greater than～12 fC based on the APV25 chip,while the time resolution is better than～1 ns(RMS)at an input charge of over～48 fC based on the AGET and STCF ASIC chips,and the equivalent noise charge is better than～0.5 fC(RMS)@20 pF based on the three ASICs.The test results indicate that the prototype readout electronics design meets the requirement of the future RICH PID detector and thus provides a reference for future engineering.

环形成像切伦科夫(RICH)探测器作为超级陶粲装置(STCF)带电强子(π/K/p)鉴别的技术选项之一,采用厚型气体电子倍增器+微网格气体(THGEM+Micromegas)混合探测器结构以实现对切伦科夫光的探测.针对RIC H原型探测器的信号读出,构建了一套1024通道测试电子学系统,并与探测器进行了联合测试.该测试电子学系统使用高密接插件与RIC H原型探测器进行连接,探测器输出信号通过测试电子学系统上的AGET和ADC芯片进行放大、成形和波形数字化,输出的数据经FPGA处理后通过千兆以太网传输至后端PC并进行数据分析.测试结果表明,在120 fC输入动态范围下,系统的等效噪声电荷(ENC)小于0.3 fC,且具有良好的输入-输出线性.该系统成功应用于RIC H原型探测器切伦科夫成像束流实验中,并取得了良好的切伦科夫光成像结果.