This paper presents a 13-bit 30 Ms/s two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with comparator offset calibration and background gain calibration. To address the impact of comparator offset on the overall ADC redundancy range, this paper proposes a calibration scheme for comparator offset. This scheme generates a calibration voltage through an R-2R calibration resistor array, which is applied to the input calibration transistor of the dynamic comparator to cancel the offset. In the pipelined analog-to-digital converter (ADC), the gain variation of the residual amplifier (RA) affects the overall performance of the ADC. This paper employs a digital background calibration technique based on Pseudo-Noise (PN) injection to track the gain variation of the amplifier. The chip is fabricated in a 40 nm process, operates at supply voltages of 1.1 V, and achieves a SNDR of 67.07 dB and an SFDR of 83 dB.

This paper presents a 10-bit 50-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 40-nm CMOS technology. A calibration technique is proposed that enables simultaneous extraction of all capacitor weights without requiring an auxiliary calibration digital-to-analog converter (DAC). An on-chip multi-bit pseudo-random number (PN) excitation is injected at power-up, and two opposite perturbations are employed to establish identifiable weight equations, which are solved using the least-mean-square (LMS) algorithm. The extracted weights are applied during normal conversion to compensate for capacitor mismatch without sacrificing effective sampling rate. Furthermore, a robust register logic is developed to minimize timing delays while mitigating the impact of PVT variations. The prototype achieves an improvement in spurious-free dynamic range (SFDR) from 56.94 dB to 78.4 dB at a sampling rate of 50 MS/s with a nyquist input signal. It consumes 0.76 mW and occupies a core area of 0.13 mm2, achieving a Schreier FoM of 40.9 fJ/conversion-step.

This work demonstrates a second-order noise-shaping SAR ADC utilizing a dynamic closed-loop amplifier and mismatch error shaping. The amplifier synergizes closed-loop precision with dynamic operation, achieving PVT-robust performance. A second-order loop filter provides 30 dB in-band noise suppression through active integration. The active summing amplifier architecture eliminates parasitic capacitance coupling inherent in passive networks while suppressing input-referred noise through gain-stage isolation. The proposed digital-domain mismatch error shaping (MES) technique for handling redundant bits mitigates the nonlinearity of the DAC capacitor by spectral redistribution. Simulated in 40-nm CMOS, the SAR ADC attains 83 dB SNDR and 89 dB SFDR over 200 kHz bandwidth at 16× OSR, consuming 0.525 mW. The figure of merit (FOM) value reaches 20 fJ/conversion-step, respectively, advancing precision ADCs for low-bandwidth sensing applications.

This paper presents a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) utilizing dynamic amplifiers and data-weighted averaging (DWA) techniques. The noise-shaping is achieved by combining finite impulse response (FIR) and infinite impulse response (IIR) filters. Dynamic amplifiers replace traditional operational transconductance amplifiers to reduce power consumption. A bidirectional-select DWA technique is proposed to address capacitor mismatch issues in 3 MSBs. The prototype chip, fabricated in a 40 nm CMOS process, operates at a voltage of 1.1 V with a sampling rate of 5 MS/s, consuming 303.2 mu W of power. With an oversampling ratio (OSR) of 8, the noise-shaping SAR ADC achieves a peak Schreier figure of merit (FOM) of 166.2 dB and a signal-to-noise and distortion ratio (SNDR) of 76.05 dB.

This paper presents a dynamic charge compensation technique to address power-area trade-offs in reference generation circuitry for successive approximation register (SAR) analog-to-digital converters (ADCs). By implementing hierarchical compensation stages and a split-capacitive DAC (split-CDAC) architecture, the proposed method overcomes limitations of conventional approaches including exponential logic complexity, capacitor mismatch, and parasitic effects. The compensation scheme combines parasitic cancellation, coarse compensation, and fine compensation to stabilize reference voltage variations while optimizing precision-complexity trade-offs. A 12-bit 80 MS/s SAR ADC demonstrates 11.16-bit ENOB and 78.05 dBc SFDR with only 7.6% additional decoupling capacitance and 2.6% power overhead, achieving 3.26-bit ENOB improvement and 21.12 dB SFDR enhancement compared to uncompensated operation. Simulation results validate the effectiveness of suppressing code-dependent reference voltage droop while maintaining CMOS compatibility, providing a scalable solution for high-speed Nyquist ADCs.

This work presents a 14-bit 100 MS/s Pipelined Successive-Approximation-Register (SAR) ADC in a 28nm CMOS process. The proposed calibration technique remedies the offset voltage and bit-weight deviations that include capacitor mismatches and inter-stage gain error. The comparator offset calibration scheme employs a shift-bit logic together with an R-2R digital-to-analog converter (DAC). An improved SAR logic circuit is also proposed to generate asynchronous timing and store the results. The capacitor mismatches are calibrated in a foreground way while the inter-stage gain error is corrected in a background way using least mean square (LMS) algorithm. With the above calibration and circuit techniques, the spurious-free-dynamic-range (SFDR) is improved to 90.64dBc, while the effective-number-of-bits(ENOB) is 11.89-bit. The 14-bit 100 MS/s ADC is simulated in a 28nm CMOS process and the figure of merit (FOM) value achieves 10.86 fJ/conversion-step.

This paper introduces a calibration technique for capacitor mismatches in a Successive Approximation Register (SAR) ADC, based on the Least Mean Square (LMS) algorithm. The Capacitor Digital-to-analog Converter (CDAC) in a SAR ADC is reused and driven by a Pseudo-Random (PN) sequence generator, generating on-chip analog input signals for LMS calibration. A dynamic iteration step size is implemented to increase convergence speed and accuracy. The calibration circuit does not sacrifice the conversion speed or significantly increase the hardware as traditional LMS-based calibration techniques. The calibration technique is verified based on a 14-bit SAR ADC model. Compared with the results before calibration, this work improve the Spurious Free Dynamic Range (SFDR) performance from 63.4dbc to 106.5dbc. Additionally, the Integral Nonlinearity (INL) performance improved from 50LSBs to 2LSBs.

This paper presents a calibration technique for capacitor mismatches and inter-stage gain error in a pipelined-SAR ADC. Foreground calibration scheme is employed for capacitor mismatches that are immune to voltage-temperature (VT) variations while a background calibration method is used to obtain the coefficient of the inter-stage gain. The proposed hybrid calibration technique is independent of the input signal distribution. Moreover, common mode voltage can be avoided by splitting the capacitors in the digital-to-analog-converter (DAC), thereby saving hardware while maintaining the calibration accuracy. The residue voltage swings are the same in both foreground and background calibration modes through the use of a split switching method, and hence the inter-stage amplifier linearity is not degraded. Simulation results show that, based on 14-bit 100MS/s pipelined-SAR ADC structure, the spurious-free dynamic range (SFDR) can reach l08.5dbc and signal to interference plus noise ratio (SNR) can reach 85.7db after using the proposed calibration method.

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a $0.18~\mu \text{m}$ CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is proposed. The auxiliary-capacitor based calibration technique eliminates the need for a dedicated reference buffer to generate the calibration voltages at all the comparator thresholds. By switching the auxiliary capacitor and doing some simple calculation work, all the capacitor mismatches in the first and second stages are corrected in the digital domain, thereby significantly improving the ADC performance. Measurement results show that, with 70.1 MHz input, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 75.5 dB to 77.8 dB, and the spurious-free-dynamic-range (SFDR) is improved from 81.9 dBc to 90.5 dBc with the proposed calibration technique.

Background Hypothermia (H), cardioplegia (CP), and both combined (HCP) are known to be protective against myocardial ischemia reperfusion (IR) injury. Mitochondria have molecular signaling mechanisms that are associated with both cell survival and cell death. In this study, we investigated the dynamic changes in proapoptotic and prosurvival signaling pathways mediating H, CP, or HCP-induced protection of mitochondrial function after acute myocardial IR injury. Methods Rats were divided into five groups. Each group consists of 3 subgroups based on a specific reperfusion time (5, 20, or 60 min) after a 25-min global ischemia. The time control (TC) groups were not subjected to IR but were perfused with 37 °C Krebs-Ringer's (KR) buffer, containing 4.5 mM K+, in a specific perfusion protocol that corresponded with the duration of each IR protocol. The IR group (control) was perfused for 20 min with KR, followed by 25-min global ischemia, and then KR reperfusion for 5, 20, or 60 min. The treatment groups were exposed to 17 °C H, 37 °C CP (16 mM K+), or HCP (17 °C + CP) for 5 min before ischemia and for 2 min on reperfusion before switching to 37 °C KR perfusion for the remainder of each of the reperfusion times. Cardiac function and mitochondrial redox state (NADH/FAD) were monitored online in the ex vivo hearts before, during, and after ischemia. Mitochondria were isolated at the end of each specified reperfusion time, and changes in O2 consumption, membrane potential (ΔΨm), and Ca2+ retention capacity (CRC) were assessed using complex I and complex II substrates. In another set of hearts, mitochondrial and cytosolic fractions were isolated after a specified reperfusion time to conduct western blot assays to determine hexokinase II (HKII) and Bax binding/translocation to mitochondria, cytosolic pAkt levels, and cytochrome c (Cyto-c) release into the cytosol. Results H and HCP were more protective of mitochondrial integrity and, concomitantly, cardiac function than CP alone; H and HCP improved post-ischemic cardiac function by (1) maintaining mitochondrial bioenergetics, (2) maintaining HKII binding to mitochondria with an increase in pAkt levels, (3) increasing CRC, and (4) decreasing Cyto-c release during reperfusion. Bax translocation/binding to mitochondria was unaffected by any treatment, regardless of cardiac functional recovery. Conclusions Hypothermia preserved mitochondrial function and cardiac function, in part, by maintaining mitochondrial bioenergetics, by retaining HKII binding to mitochondria via upstream pAkt, and by reducing Cyto-c release independently of Bax binding to mitochondria.

This paper presents a 10-b 500MS/s successiveapproximation-register (SAR) analog-to-digital converter (ADC) designed using a 40nm CMOS process. The first 6-bit coarse conversion is completed by a high speed loop-unrolled architecture, while the succeeding 5 bits are obtained by a traditional SAR structure. A foreground calibration is employed to correct the offsets in the six comparators of the coarse converter, while the residual errors due to process-voltage-temperature (PVT) variations are covered by 1-bit redundancy. A background offset calibration technique based on alternate comparators is proposed, which tracks PVT variations while eliminating a dedicated calibration phase. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) can achieve 60.30dB and 68.95dBc, respectively. The power consumption of the whole system is 4.164mW under 1.1V supply voltage, thereby obtaining a figure of merit (FoM) of 9.87fJ/conv.-step.

This brief proposes a high spurious-free dynamic range (SFDR) pulse output direct digital frequency synthesizer (PDDS) with low complexity and low power consumption. Independent and uniformly distributed (IUD) high-pass-shaped dither is added to the phase accumulator output, resulting in a wideband spurious-free and low close-in noise floor. The power efficiency and speed are increased by reducing the sampling frequency of the ${m}$ -sequence generator and the high-pass filter (HPF). The SFDR improves by 29 dB as a result of the HPF, which is confirmed with a field-programmable gate array (FPGA) implementation. The application specified integrated circuit (ASIC) occupies $1168~{\mu \text {m}^{2}}$ on nangate 45-nm CMOS process and consumes 80.2 and $398~{\mu }\text{W}$ from a 1.2-V supply with the dither generator running at ${({1}/{4})f_{\text {clk}}}$ and ${f_{\text {clk}}}$ ( ${f_{\text {clk}}}=2$ GHz), respectively.

This brief proposes adaptive dither windows to calibrate bit weights in pipelined analog-to-digital converters (ADCs). It exploits the comparator meta-stability nature to construct dither windows, which avoids doubling the number of the comparators. The dither window size as defined by the sub-ADC comparator metastability region is tightly controlled and adapted to process-voltage-temperature (PVT) variations by adjusting the digitally controlled delay lines (DCDLs) against a capacitor-ratio reference. Besides, it cancels the voltage swing increment due to the dither windows, which relieves the design of the residue amplifier and saves the over-range margin of the stage. The proposed calibration technique is demonstrated by using a 12-bit pipelined ADC in a 40 nm CMOS process, and simulation results show that the window size is adjusted adaptively under PVT corners while the voltage swing increment is cancelled. The spurious-free-dynamic-range (SFDR) and the signal-to-noise-and-distortion-ratio (SNDR) are improved from 61.8 dB and 53 dB to 92 dB and 73.6 dB, respectively.

This paper presents an asynchronous 2-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). The offset mismatches among the three comparators are background calibrated by quantizing the same residue signal during the last 1-bit cycle. It eliminates the dependence on the signal distribution and utilizes the following sampling phase for the settling of the calibration voltages. An asynchronous timing sequence is also proposed to avoid an external high speed clock generator. A design example of 8-bit 500 MS/s SAR ADC in 40nm CMOS technology is presented. Simulation results show that with Nyquist input, the spurious-free-dynamic-range (SFDR) achieves 62 dB while the effective number of bits (ENOBs) is 7.6 bits.

BACKGROUND/AIMS:The role of VDAC1, the most abundant mitochondrial outer membrane protein, in cell death depends on cell types and stimuli. Both silencing and upregulation of VDAC1 in various type of cancer cell lines can stimulate apoptosis. In contrast, in mouse embryonic stem (MES) cells and mouse embryonic fibroblasts (MEFs), the roles of VDAC1 knockout (VDAC1-/-) in apoptotic cell death are contradictory. The contribution and underlying mechanism of VDAC1-/- in oxidative stress-induced cell death in cardiac cells has not been established. We hypothesized that VDAC1 is an essential regulator of oxidative stress-induced cell death in H9c2 cells.METHODS:We knocked out VDAC1 in this rat cardiomyoblast cell line with CRISPR-Cas9 genome editing technique to produce VDAC1-/- H9c2 cells, and determined if VDAC1 is critical in promoting cell death via oxidative stress induced by tert-butylhydroperoxide (tBHP), an organic peroxide, or rotenone (ROT), an inhibitor of mitochondrial complex I by measuring cell viability with MTT assay, cell death with TUNEL stain and LDH release. The mitochondrial and glycolytic stress were examined by measuring O2 consumption rate (OCR) and extracellular acidification rate (ECAR) with a Seahorse XFp analyzer.RESULTS:We found that under control conditions, VDAC1-/- did not affect H9c2 cell proliferation or mitochondrial respiration. However, compared to the wildtype (WT) cells, exposure to either tBHP or ROT enhanced the production of ROS, ECAR, and the proton (H+) production rate (PPR) from glycolysis, as well as promoted apoptotic cell death in VDAC1-/- H9c2 cells. VDAC1-/- H9c2 cells also exhibited markedly reduced mitochondria-bound hexokinase II (HKII) and Bax. Restoration of VDAC1 in VDAC1-/- H9c2 cells reinstated mitochondria-bound HKII and concomitantly decreased tBHP and ROT-induced ROS production and cell death. Interestingly, mitochondrial respiration remained the same after tBHP treatment in VDAC1-/- and WT H9c2 cells.CONCLUSION:Our results suggest that VDAC1-/- in H9c2 cells enhances oxidative stress-mediated cell apoptosis that is directly linked to the reduction of mitochondria-bound HKII and concomitantly associated with enhanced ROS production, ECAR, and PPR.

This brief presents a two stage open loop fractional-N frequency synthesizer using proposed injection locking phase modulator for low power applications. A novel low power injection locking oscillator (ILO)-based digital phase modulator (DPM) is proposed in this brief. The maximum differential nonlinearity (DNL) of proposed DPM is smaller than 0.3 degree in the whole range with 1.6 mW power consumption. An integer-N injection locking phase locked loop (ILPLL) is designed to generate the radio frequency signals for the second stage open loop frequency synthesizer. With an injection strength adjustment unit, the open loop fractional-N frequency synthesizer employing proposed DPM achieved excellent in band phase noise and instantaneous frequency switching with low power consumption. This frequency synthesizer is fabricated on 28-nm CMOS technology and its active area is 0.08 mm 2 . The output frequency range is from 320 MHz to 520 MHz and the power dissipation is 2.7 mW from 0.9 V supply in fractional-N mode. The measured RMS jitter integrated phase noise from 10 KHz to 40 MHz of 440 MHz and 440.4 MHz carrier frequency are 3.8 ps and 17.6 ps, respectively. The corresponding figure of merits (FoM) are -231 dB and -211 dB, respectively.

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches.

A shaping technique is proposed to remedy the attenuation-factor error in the split capacitor-digital-to-analogue converter (CDAC) of a successive-approximation-register (SAR) ADC. By feeding back the previous quantised value of the least significant bit part to the most significant bit part, the inaccurate attenuation-factor error caused by mismatches and parasitic components is shaped to high frequency. The in-band dynamic performance is significantly improved without any calibration. Simulation results show that the proposed attenuation-factor shaping technique improves the spurious-free-dynamic-range by 10 dB, whereas the number of capacitors increases only 1.2%.

A background calibration technique is proposed to correct bit weights in pipelined-successive-approximation-register (SAR) analogue-to-digital converters (ADCs). By splitting the second stage, the input signal interference is mostly removed, thereby greatly enhancing the convergence speed of the algorithm. Besides, the dither signal assists to eliminate mismatch issues between the partially split ADCs, thus relaxing the analogue overheads. According to the simulation, after calibration, the spurious-free-dynamic-range and signal-to-noise-and-distortion-ratio are improved from 53.2 to 88.2 dB and 49.5 to 75.2 dB, respectively. The calibration algorithm converges with about only 600 K samples.

非参数数据包络分析方法在能源与环境效率评估、污染物影子价格估计、排放权分配等领域获得了广泛应用,其建模的一个重要理论基础是环境生产技术的表征.本文对非参数环境生产技术的理论、模型及应用做了较为系统的回顾与展望.首先,从非期望产出处置方式的角度对常见的非参数环境生产技术进行总结分类,指出各类环境生产技术的关键特征和内在局限.其次,从可处置性、应用领域、污染物种类等方面,系统总结了环境生产技术的最新研究进展,对以环境生产技术为基础的应用研究的特征做了归纳.最后,指出环境生产技术未来可能的研究方向,以期推动环境生产技术相关理论研究和实践应用.