The Internet of Things leverages Internet technology in cyber-physical systems (CPSs), but the protocols and principles of the Internet were designed for interacting with information systems, not cyber-physical systems. For one, timeliness is not a factor in any widespread Internet technology, with quality-of-service features having been routinely omitted for decades. In addition, for things, safety, freedom from physical harm, is even more important than information security, the focus on the Internet. Nevertheless, properties of the Internet are valuable in CPSs, including a global namespace, reliable (eventual) delivery of messages, end-to-end security through asymmetric encryption, certificate-based authentication, and the ability to aggregate data from a multiplicity of sources in the cloud. This paper discusses and surveys architectural approaches, communication protocols, and programming models that promise to bridge the gap, enabling the use of the Internet technologies even in safety-critical, cyber-physical applications such as factory automation and transportation. Specifically, we argue that smart gateways hosted on edge computers complement cloud-based services; they can provide tighter control over timing and security that is robust against network outages, play an active role in managing interactions between things, and isolate safety-critical services from best-effort services. We explain how time sensitive network technology can be leveraged to reliably orchestrate a multiplicity of things, and how augmenting our programming models with a well-defined notion of time can make systems more deterministic and more testable.

Formal specifications on temporal behavior of Cyber-Physical Systems (CPS) is essential for verification of performance and safety. Existing solutions for verifying the satisfaction of temporal constraints on a CPS are compute and resource intensive since they require buffering signals from the CPS prior to constraint checking. We present an online approach, based on Timestamp Temporal Logic (TTL), for monitoring the timing constraints in CPS. The approach reduces the computation and memory requirements by processing the timestamps of pertinent events reducing the need to capture the full data set from the signal sampling. The signal buffer size bears a geometric relationship to the dimension of the signal vector, the time interval being considered, and the sampling resolution. Since monitoring logic is typically implemented on Field Programmable Gate Arrays (FPGAs) for efficient monitoring of multiple signals simultaneously, the space required to store the buffered data becomes the limiting resource. The monitoring logic, for the timing constraints on the Flying Paster (a printing application requiring synchronization between two motors), is illustrated in this paper to demonstrate a geometric reduction in memory and computational resources in the realization of an online monitor.

Time is a foundational aspect of Cyber-Physical Systems (CPS). Correct time and timing of system events are critical to optimized responsiveness to the environment, in terms of timeliness, accuracy, and precision in the knowledge, measurement, prediction, and control of CPS behavior. However, both the specification and verification of timing requirements of the CPS are typically done in an ad-hoc manner. While feasible, the system can become costly and difficult to analyze and maintain, and the process of implementing and verifying correct timing behavior can be error-prone. Towards the development of a verification testbed for testing timing behavior in tools and platforms with explicit time support, this paper first describes a way to express the various kinds of timing constraints in distributed CPS. Then, we outline the design and initial implementation of a distributed testbed to verify the timing of a distributed CPS analytically through a systematic framework. Finally, we illustrate the use of the verified timing testbed on two distributed CPS case studies.

In order to test the performance and verify the correctness of Cyber-Physical Systems (CPS), the timing constraints on the system behavior must be met. Signal Temporal Logic (STL) can efficiently and succinctly capture the timing constraints of a given system model. However, many timing constraints on CPS are more naturally expressed in terms of events on signals. While it is possible to specify event-based timing constraints in STL, such statements can quickly become long and arcane in even simple systems. Timing constraints for CPS, which can be large and complex systems, are often associated with tolerances, the expression of which can make the timing constraints even more cumbersome using STL. This paper proposes a new logic, Timestamp Temporal Logic (TTL), to provide a definitional extension of STL that more intuitively expresses the timing constraints of distributed CPS. TTL also allows for a more natural expression of timing tolerances. Additionally, this paper outlines a methodology to automatically generate logic code and programs to monitor the expressed timing constraints. Since our TTL monitoring logic evaluates the timing constraints using only the timestamps of the required events on the signal, the TTL monitoring logic has significantly less memory footprint when compared to traditional STL monitoring logic, which stores the signal value at the required sampling frequency. The key contribution of this paper is a scalable approach for online monitoring of the timing constraints. We demonstrate the capabilities of TTL and our methodology for online monitoring of TTL constraints on two case studies: 1) Synchronization and phase control of two generators and, 2) Simultaneous image capture using distributed cameras for 3D image reconstruction.

Many modern cyber-physical systems (CPS), especially industrial automation systems, require the actions of multiple computational systems to be performed at much higher rates and more tightly synchronized than is possible with ad hoc designs. Time is the common entity that computing and physical systems in CPS share, and correct interfacing of that is essential to flawless functionality of a CPS. Fundamental research is needed on ways to synchronize clocks of computing systems to a high degree, and on design methods that enable building blocks of CPS to perform actions at specified times. To realize the potential of CPS in the coming decades, suitable ways to specify distributed CPS applications are needed, including their timing requirements, ways to specify the timing of the CPS components (e.g. sensors, actuators, computing platform), timing analysis to determine if the application design is possible using the components, confident top-down design methodologies that can ensure that the system meets its timing requirements, and ways and methodologies to test and verify that the system meets the timing requirements. Furthermore, strategies for securing timing need to be carefully considered at every CPS design stage and not simply added on. This paper exposes these challenges of CPS development, points out limitations of previous approaches, and provides some research directions towards solving these challenges.

A new economy built on the massive growth of endpoints on the internet will require precise and verifiable timing in ways that current systems do not support.Applications, computers, and communications systems have been developed with modules and layers that optimize data processing but degrade accurate timing.State-of-the-art systems now use timing only as a performance metric.Correctness of timing as a metric cannot currently be designed into systems independent of hardware and/or software implementations.To enable the massive growth predicted, accurate timing needs cross-disciplinary research to be integrated into these existing systems.This paper reviews the state of the art in six crucial areas central to the use of timing signals in these systems.Each area is shown to have critical issues requiring accuracy or integrity levels of timing, that need research contributions from a range of disciplines to solve.

Timing and synchronization play a key role in cyber-physical systems (CPS). Precise timing, as often required in safety-critical CPS, depends on hardware support for enforcement of periodic measure, compute, and actuate cycles. For general CPS, designers use a combination of application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs) and conventional microprocessors. Microprocessors as well as commonly used computer languages and operating systems are essentially devoid of any explicit support for precise timing and synchronization. Modern computer science and microprocessor design has effectively removed time from the abstractions used by designers with the result that time is regarded as a performance metric rather than a correctness specification or criterion.There are interesting proposals and avenues of research to correct this situation, but the barrier is quite high for conducting proof of concept studies or collaborative research and development. This paper proposes a conceptual design and use model for a reconfigurable testbed designed specifically to support exploratory research, proof of concept, and collaborative work to introduce explicit support for time and synchronization in microprocessors, reconfigurable fabrics, language and design system architecture for time-sensitive CPS.Reconfigurable computing is used throughout the system in several roles: as part of the prototyping platform infrastructure, the measurement and control system, and the application system under test.

Distributed cyber-physical systems (CPS) are increasingly provided with an accurate and precise common sense of time using a variety of well established time distribution methods such as GNSS, IEEE 1588 and others. Less attention has been paid to the effective use of time in CPS and techniques and components to support such use. This paper reviews these topics and discusses critical components that are needed. If this infrastructure is properly realized recent work suggests that subject to well defined constraints, it will be possible to design CPS where timing is correct-by-construction.

Forms of synchrony can greatly simplify modeling, design, and verification of distributed systems. Thus, recent advances in clock synchronization protocols and their adoption hold promise for system design. However, these protocols synchronize the distributed clocks only within a certain tolerance, and there are transient phases while synchronization is still being achieved. Abstractions used for modeling and verification of such systems should accurately capture these imperfections that cause the system to only be “almost synchronized.” In this paper, we present approximate synchrony, a sound and tunable abstraction for verification of almost-synchronous systems. We show how approximate synchrony can be used for verification of both time synchronization protocols and applications running on top of them. We provide an algorithmic approach for constructing this abstraction for symmetric, almost-synchronous systems, a subclass of almost-synchronous systems. Moreover, we show how approximate synchrony also provides a useful strategy to guide state-space exploration. We have implemented approximate synchrony as a part of a model checker and used it to verify models of the Best Master Clock (BMC) algorithm, the core component of the IEEE 1588 precision time protocol, as well as the time-synchronized channel hopping protocol that is part of the IEEE 802.15.4e standard.

Since the publication of IEEE 1588-2008 the number of applications based on the standard has exploded. The standard is currently open for revision and will result in incorporation of improvements and simplifications based on the experience since 2008. In the realm of cyber-physical systems, CPS, there is growing awareness that robust solutions must include the consideration of time. This is evidenced by activity in recently constituted industry and quasi-standards organizations which at least in part has been stimulated by progress and adoption of 1588 and of the specialized profiles derived from 1588. This paper will review these developments and activities and highlight needed future developments.

This paper studies conditions where messages endlessly circulate in a system of IEEE 1588-2008 clocks. The study is based on two independent analysis techniques. One uses a discrete event simulation environment for describing the operation of the best master clock (BMC) algorithm in IEEE 1588-2008. The second uses a model checking tool. We discuss several cases illustrating conditions under which circulating messages occur and the effectiveness of measures to squelch these messages. This paper demonstrates that one or more of the squelching mechanisms must be implemented.

: This paper discusses the use of the Ptides model of computation as a coordination language for the design of deterministic, event-driven, real-time, distributed embedded systems. Specifically, the paper shows how the use of synchronized clocks in the context of Ptides enables explicit, platform independent specification of functionality and timing. From this specification we generate code for two target platforms: Renesas and XMOS. The generated code includes a lightweight operating system which performs scheduling, I/O and network handling as well as application specific tasks. Ptides models are developed in Ptolemy, a design and simulation environment for heterogeneous systems. This framework also contains a code generation framework which is leveraged to derive Ptides implementations from the models. We illustrate our approach by designing a simple Ptides application, a small component in a printing press responsible for on-the- y changeover between paper rolls. We demonstrate the design process and show that the generated code exhibits identical timing at the cyber-physical boundary on multiple implementation platforms.

This is a chapter from the book System Design, Modeling, and Simulation using Ptolemy II This work is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License. To view a copy of this license, visit: http://creativecommons.org/licenses/by-sa/3.0/, or send a letter to Creative Commons, 444 Castro Street, Suite 900, Mountain View, California, 94041, USA. Permissions beyond the scope of this license may be available at: http://ptolemy.org/books/Systems.

This paper reviews the use of time, clocks, and clock synchronization protocols in cyber-physical systems (CPS). Recent advances in the area of timing suggest avenues of research and potential new application areas. We discuss how introducing timestamps and clocks can help overcome issues such as latency, jitter, and determining correct execution order. Furthermore, we show how system complexity can be reduced and distribution as well as parallelism can be done deterministically. We also point to recent work in raising time to first class citizen status in modeling and implementation. In particular, we describe design and execution environments of CPS and specialized hardware such as predictable timing architectures where time plays a key role.

This paper describes a model-based design approach for deterministic, event-driven real-time controllers. The model, called Ptides, allows for explicit, platform independent specification of functionality and timing. From this specification, code is generated for given target platforms. The generated code includes a lightweight operating system which performs I/O handling and scheduling as well as application specific tasks. Currently, code can be generated for 3 different platforms: a Luminary Micro board, a Renesas board and an XMOS board.

PTIDES, a programming model for distributed real-time systems, was proposed previously. The model captures both the functionality of the system and the desired timing of interactions with the environment. The PTIDES simulator supports simulation of both of these aspects. In this work, we focus on the PTIDES development environment in the context of applications drawn from the control of electric power systems. The evaluation is based on experiments on a system of distributed computing platforms emulating typical power system control and monitoring devices and an emulation of portions of the electric power grid based on conventional micro-controller instrumentation.

A common sense of time among the elements of a distributed measurement and control system allows the use of new techniques in solving problems with complex synchronization requirements or arising from the interaction of many sensors and actuators. Such a common sense of time may be accomplished using the standard IEEE 1588-2002 to synchronize real-time clocks integral to each component of the system. IEEE 1588, expands the performance capabilities of Ethernet networks so that they become relevant for measurement and control; this monograph embodies the first unified treatment of the associated technology, standards and applications. Readers will gain understanding of the technological context of IEEE 1588 and its role in a variety of application settings. To engineers this monograph provides detailed discussion of the complex features of the standard. Together with the essential material on best practice and implementation issues, these provide invaluable assistance in the design of new applications.