Dynamic reconfiguration of digital circuits on FPGAs has been an area of active research for the past decade. The identification of generic classes of circuits that would benefit from being dynamically reconfigured remains a key, open problem. We report on an investigation of the application of dynamic reconfiguration to programmable, multi-function cores (PMCs). An abstract analysis of the technique is included to emphasise the generality of the methodology. Empirical results for a case study involving a universal asynchronous receiver and transmitter (UART) are presented. We show that significant improvements in area efficiency and the operating speeds of the circuits are achieved. Furthermore, the results indicate the potential for reducing the power consumption of the circuits.

FPGA technology has progressed to the point where complete digital systems can be configured on to a single device. The design complexity of integrating entire systems on FPGA platforms mandates the extensive re-use of intellectual property (IP) cores. This paper investigates the dynamic reconfiguration of IP cores for FPGAs to improve their area, timing and power characteristics. We report a class of cores that will benefit from this technique and present a methodology for the design of these dynamically reconfigurable IP (DRIP) cores. A case study of a universal asynchronous receiver transmitter (UART) is presented to demonstrate the methodology and quantify the improvements in quality of results (QoR). The UART DRIP core has been synthesised for several FPGA devices with results indicating area improvements that are substantially independent of device architecture. Finally, analysis of an Infra-red Data Association (IrDA) controller establishes the potential for even greater improvements in QoR with more complex IP cores.

The use of reconfiguration of field programmable gate arrays (FPGAs) to improve the area efficiency of a class of FPGA circuits is reported. The applicability of the technique to a large class of general-purpose applications is established by identifying the key characteristics of suitable circuits. The development of a new design methodology that allows the technique to be reliably deployed with repeatable results is described. The claims for improved area efficiency are supported by analysis of the design and empirical results of a case study involving a universal asynchronous transmitter receiver (UART). The empirical results point to the potential for further performance improvements in the power consumption of the experimental circuits.