Unlike SiO2-based devices, various structural defects and small band gaps in high-κ gate dielectrics make high-κ devices susceptible to electron charging. In particular, fast transient charging in high-κ devices was shown to distort the outcome of reliability tests because conventional stress and sense method cannot account for the charge decay during the delay between stress and sense. In this paper, the effect of transient charging on hot carrier stress and bias temperature instability tests of high-κ devices will be examined and the technical challenges inherent in these tests will be discussed.

The optimization of MOSFET performance with Hf-based high-k and TiN metal gate is discussed. MOSFET performance and mobility of metal and poly gate on both high-k and SiO2 are compared. Optimization of the thickness and composition of Hf-silicate is discussed in terms of charge trapping and boron diffusion. The effect of metal gate thickness is also investigated. Appropriate dry and wet etch processes are found to effectively eliminate the metal foot and high-k undercut. Impressive Ion- Ioff characteristics have been achieved by applying an optimized gate-first CMOS flow to the high-k/metal stack. Ion = 1100µA/µm and 540µA/µm was attained for N and PMOSFETs with Vdd = 1.2V and Ioff = 100nA/µm.

Fast transient and relatively slow constant voltage stress (CVS) electron trapping phenomena in high-k gate dielectrics are investigated. It is suggested that the resonance tunneling of the injected electrons directly into the shallow defect states is responsible for the fast transient trapping, while the temperature-activated electron migration between the traps govern slow CVS trapping. The extracted trap energies and their effective dimensions fit the calculated characteristics of the O vacancies in monoclinic hafnia. The relationship between trap characteristics and the reduction of trapping observed in ultra- thin high-k gate stacks is discussed.

Effect of NH3 predeposition anneal (pre-DA) temperature prior to ultrathin atomic layer deposition (ALD) HfO2 deposition (15–30 Å) on equivalent oxide thickness (EOT) and mobility of TiN∕HfO2∕Si metal-oxide field effect transistors has been studied systematically. At the same physical thickness, reduction of EOT by high temperature NH3 pre-DA treatment (∼900°C) has been achieved, with no apparent change in Jg (leakage current density), though no significant channel mobility reduction could be observed. Increase in nitrogen content with pre-DA temperature improved overall dielectric constant and bulk trapping immunity, though slight mobility reduction was attributed to positive charge pile up at the interface. The ultrathin EOT (∼7.4Å) with good mobility values sets ALD HfO2 as a very promising candidate for alternate gate oxide.