A novel stress-anneal approach has been investigated to separate the role of electrons and hole charge trappings in Hf-based gate oxides. It is observed that heat treatment following a stress experiments on Hf-based MOSFET can effectively eliminate electron trapping in the oxide. We also report that hole accumulation in the bulk of the Hf-based dielectrics is primarily responsible for dielectric breakdown, though both holes and electrons are trapped in the dielectrics. The Si interface quality does not seem to degrade significantly.

Transient relaxation, which has been addressed as an undesirable issue in high-k alternate gate dielectrics, has been studied systematically. In Hf-based dielectrics, it follows a universal line irrespective of stress times and stress voltages if stressed (static/dynamic) up to certain limits. The results presented here reveal that bulk charge trapping shows a fast transient relaxation (TR) for a very short time (/spl sim/ ms) after stress (substrate injection) followed by a slow relaxation (> 1 s), while interface passivation/relaxation follows a slow trend. Bulk trappings, which play a major role in causing device instabilities in high-k gate oxides, are mostly relaxable, while interface degradation cannot be passivated completely. Moreover, an interface-passivation mechanism seems to be independent of stress histories. Devices with stronger bulk-trapping immunity showed faster TR. The experimental results show good agreement with the simplified mathematical model presented for HfO/sub 2/ gate oxides. The temperature showed a negligible effect in TR.

We report that precursor HfCl4 plays an important role in optimizing atomic-layer-deposition HfO2 bulk trapping characteristics. By systematic study, it has been observed that, under certain optimized precursor pulse time condition (450ms pulse as compared to standard 150ms), bulk trapping characteristics could be improved significantly without affecting the equivalent oxide thickness and leakage current characteristics of the devices. Slight improvement in mobility of the devices could also be obtained. Secondary-ion-mass-spectroscopy analysis shows that increase in the chlorine composition by increasing precursor pulse time could be attributed to the observed improvement. Drastic increase in pulse time (1500ms) negates the benefit.

The effect of a bi-layer structure by varying the Hf composition in Hf-silicate dielectric in improving the electrical performance and reliability of high-/spl kappa/ gate stack n-MOSFETs has been investigated. Introducing Hf-silicate with 19.5% of Hf composition at the bottom layer and 28.5% of Hf on the top of it reduces the leakage current dramatically, while it minimally sacrifices increase in equivalent oxide thickness. Moreover, the structure reduces defect generation rate under gate injection and improves breakdown voltage in comparison to the control samples. Increase in Si-O bonds at the bottom interface, decrease in Coulomb scattering, and increase in dielectric constant in the top layer have been attributed to the overall performance increase of the gate stack.

The effect of deionized water and dilute hydrochloric acid, 500:1 (HCl) post-Hf-silicate deposition cleaning on the device characteristics of Hf-silicate MOSFETs have been investigated. The results suggest that a significant improvement in mobility and equivalent oxide thickness scaling can be obtained using HCl post-treatment in comparison to control and H/sub 2/O post-treated devices. The enhancement in bulk trapping immunity has been attributed to the reduced charge trapping in the bulk high-/spl kappa/ layers, whereas no apparent change in interface properties could be observed. The effect of the post-deposition cleaning might have important implications on the wet etching of gate metals in dual-metal-gate technology.

The effects of H/sub 2/O and HCl post-clean after Hf-silicate deposition in improving bias instability, reliability and mobility of CMOS devices have been demonstrated. It was found that HCl post-treatment reduced charge trapping, thus improved bias instabilities, but had no effect on interface traps. High pressure H/sub 2/ anneal improved interface states significantly, with no effect on bulk traps at all.

This Letter reports the nickel-silicide phase effects on the electrical characteristics of high-k and silicon dioxide (SiO2) metal-oxide-semiconductor devices. It was found that the silicon-deficient nickel-silicided gate electrode on the hafnium silicon oxynitride (HfSiON) led to a positive flatband voltage (Vfb) shift and a reduction in the equivalent oxide thickness (EOT). However, negligible Vfb shift and EOT decrease were observed in the case of control hafnium oxide and SiO2 structures. It was believed that Si dissociation from the HfSiON layer was the main reason for the positive Vfb shift and the EOT decrease.

We report that post-deposition rinsing of metalorganic-chemical-vapor-deposited Hf-silicate dielectric with HCl (500:1) improves mobility, bias instabilities, and stress-induced leakage current of metal-oxide-semiconductor field-effect transistors. Reduction of bulk charge trapping has primarily been attributed to this improvement. High-pressure H2 anneal improved interface states significantly, with no effect on bulk trapping characteristics. HCl post-treatment did not show any apparent effect on interface state properties.

N -type metal-oxide-semiconductor field-effect transistors (N-MOSFETs) using HfTaO with varying Ta composition (20%, 30%, 40%, and 50%) have been fabricated and characterized. Crystallization temperatures of HfTaO with varying Ta composition were also measured. It was found that HfTaO with 40% Ta exhibited the highest crystallization temperature of 900 °C, while 35% and 52% HfTaO showed crystallization temperature of 800 °C. The results demonstrate that HfTaO N-MOSFETs exhibit higher electron mobility than controlled HfO2 devices. Among them, the transistor with 40% Ta shows the highest electron mobility.

Optimization of TiO/sub 2//HfO/sub 2/ bi-layer dielectric MOSFETs and their breakdown behaviors have been investigated for the first time. As the ratio of TiO/sub 2/ top layer increases, reduced EOT, reduced hysteresis, and improved transistor characteristics with increasing electron and hole mobility are observed. Distribution of a two-step breakdown characteristics suggest the breakdown occurs first in the HfO/sub 2/ bottom layer.

In this letter, we present the effects of the nitrogen-incorporated interface on threshold voltage shift (ΔVth), which was induced by charge trapping and detrapping in hafnium oxide (HfO2) n-metal–oxide–semiconductor field-effect transistors. Under the various gate voltage conditions, the nitrogen-incorporated interface showed a smaller ratio of interface charge density to total charge density (Nit∕Ntotal) due to its thinner interface thickness and lower energy band offset. In addition, the degradations of the interface quality and the mobility under the stress condition were less severe for the nitrogen-incorporated interface devices.

Effect of NH3 predeposition anneal (pre-DA) temperature prior to ultrathin atomic layer deposition (ALD) HfO2 deposition (15–30 Å) on equivalent oxide thickness (EOT) and mobility of TiN∕HfO2∕Si metal-oxide field effect transistors has been studied systematically. At the same physical thickness, reduction of EOT by high temperature NH3 pre-DA treatment (∼900°C) has been achieved, with no apparent change in Jg (leakage current density), though no significant channel mobility reduction could be observed. Increase in nitrogen content with pre-DA temperature improved overall dielectric constant and bulk trapping immunity, though slight mobility reduction was attributed to positive charge pile up at the interface. The ultrathin EOT (∼7.4Å) with good mobility values sets ALD HfO2 as a very promising candidate for alternate gate oxide.

The ultrathin HfO2 gate dielectric (EOT < 0.7 nm) has been achieved by using a novel "oxygen-scavenging effect" technique without incorporation of nitrogen or other "dopants" such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO2 gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 angstrom, the thinnest EOT value reported to date for "undoped" HfO2 with acceptable leakage current, while EOT of 12.5 angstrom was obtained for the control HfO2 film with the same physical thickness after 450 1 C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to "scavenging effect" that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of similar to 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.

A stacked Y/sub 2/O/sub 3//HfO/sub 2/ multimetal gate dielectric with improved electron mobility and charge trapping characteristics is reported. Laminated hafnium and yttrium were sputtered on silicon followed by post-deposition anneal (PDA) in N/sub 2/ ambient. The new dielectric shows a similar scalability to HfO/sub 2/ reference. Analysis on flatband voltage shift indicates positive fixed charge induced by Y/sub 2/O/sub 3/. Excellent transistor characteristics have been demonstrated. Stacked Y/sub 2/O/sub 3//HfO/sub 2/, compared to HfO/sub 2/ reference with similar equivalent oxide thickness (EOT), shows 49% enhancement in transconductance and 65% increase in the peak electron mobility. These improvements may be attributed to better charge trapping characteristics of the multimetal dielectric.

A novel approach of fabricating laminated TiO/sub 2//HfO/sub 2/ bi-layer multi-metal oxide dielectric was developed for high performance CMOS applications. Both layers showed negligible intermixing and no silicide formation. For the first time, ultra-thin EOT (/spl sim/8 /spl Aring/) was achieved with increased effective permittivity (k /spl sim/ 36) using the bi-layer dielectric. Leakage current characteristic was slightly higher than HfO/sub 2/ due to lower band offset of TiO/sub 2/. However, superior thermal stability (>950/spl deg/C), significantly reduced hysteresis characteristic, and comparable interface state density represent the high quality of TiO/sub 2//HfO/sub 2/ multi-metal oxide. Also, excellent subthreshold swing, increased transconductance, higher current drive, and -33% improved channel electron mobility compared to the control HfO/sub 2/ samples demonstrate the feasibility of new multi-metal oxide application for future CMOS technology.

Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO2. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be like hafnium-silicon-oxynitride (HfSiON) while the IL of the HfO2 films seemed to be hafnium-silicate (HfSiO). HfON showed an increase of 300degreesC in crystallization temperature compared to HfO2. Dielectric constants of bulk and interface layer of HfON were 21 and 14, respectively. The dielectric constant of interfacial layer in HfON (similar to 14) is larger than that of HfO2 (similar to7.8). HfON dielectrics exhibit similar to10 x lower leakage current (J) than HfO2 for the same EOTs before post-metal anneal (PMA), while similar to40 x lower J after PMA. The improved electrical properties of HfON over HfO2 can be explained by the thicker physical thickness of HfON for the same equivalent oxide thickness (EOT) due to its higher dielectric constant as well as a more stable interface layer. Capacitance hysteresis (DeltaV) of HfON capacitor was found to be slightly larger than that of HfO2. Without high temperature forming gas anneal, nMOSFET with HfON gate dielectric showed a peak mobility of 71 cm(2)/Vsec. By high temperature forming gas anneal at 600degreesC, mobility improved up to 256 cm(2)/Vsec.

We present the threshold voltage instability characteristics of high-k HfO2 NMOSFET dielectric with SiON interface layer under dynamic stress. Compared to DC stress, reduced threshold voltage shift was observed at higher frequency and lower duty cycle in AC unipolar stress. Similarly, the degradation of maximum transconductance was also reduced with AC stress conditions. However, the degradation in subthreshold swing was found to be negligible and fairly independent of stress frequencies and duty cycles in AC unipolar stress. The traps in bulk of HfO2 dielectric, which is proportional to its physical thickness, is believed as the primary factor for larger threshold voltage shift as the thickness of HfO2 increases. Compared to the result under DC constant voltage stress, AC unipolar stress allows higher 10-year lifetime operating voltage.

In this work, we present the effects of a SiN interface on charge trapping and de-trapping characteristics and time-dependent threshold voltage instability. The use of SiN interface structure was found to reduce the degradation in D/sub it/ and G/sub m/ even though it yielded higher bulk charge trapping. The higher bulk trap was evidenced from larger after-stress V/sub th/ degradation. Thus, it is believed that mobility degradation in HfO/sub 2/ is primarily caused by the degraded quality of the interfacial layer.