The need for high-quality multi-media data increases the amount of data to be stored and processed, necessitating DDR5 to achieve high-density and high-speed with low-power consumption [1]. However, high-speed with low-power operation makes DRAM more vulnerable to process-voltage-temperature (PVT) variations, negative-bias thermal instability (NBTI), etc. In this work, a mono-die based 24-Gb high-density DDR5 achieving 6.4Gbps/pin is implemented. To lower power consumption, GIO switching is reduced by using a GIO separation switch and a read-only GIO pre-charge scheme. The proposed DRAM has a higher tolerance to NBTI, since the delay-locked loop (DLL) experiences slow toggling during self-refresh operations where the DLL is not necessary. Also, adaptive body bias (ABB) is used to combat process variation [2], thereby achieving high-performance I/O circuits. In addition, a low-pass filter is added for higher operations and sensitivities in front of charge pump, which is used by a duty cycle error detector (DCD) and a quadrature error detector (QED). Additionally, a balanced MUX and a bandwidth booster are also used in the transmitter for high-speed operations.

Abstract There are many wafer level tests, such as Fail Bit Count (FBC), where conventional statistical analysis methods are inadequate because the associated data do not follow a normal distribution. This paper introduces a statistical failure analysis technique that does not rely on location and scale parameters and is thus able to handle such cases. It describes the math on which the method is based and explains how to determine effect size (ES) using the quantile comparison equivalence criteria (QCEC) and a statistical parameter, called the center of dispersion (CoD), that distinguishes between center difference and dispersion difference. It also includes a case study showing how the new method is used to assess the effect of a process change on dynamic random access memory test data and how it compares in terms of accuracy with conventional statistical techniques.

Abstract Rapid and accurate root cause analysis of the defect contributes to improvement in yield and quality in semiconductor manufacturing system. In particular, imperfection of final test can cause major problems for customers, so analysis on root cause of final test failure is important activity for high quality. It can be started with finding first test data which is highly correlated with final test failure. However, it is difficult to analyze the correlation of first test data and final test failures because the first test is made up of hundreds of test items, and the data also show non-parametric characteristics with extreme outlier. In this study, Kolmogorov-Smirnov test (K-S test), which is a non-parametric test method, is statistically applied to the first test data. The K-S test is intuitive and descriptive, which makes it easy to analyze the root cause. And K-S test showed a performance improvement compared to t-test statistic, which requires a normal distribution assumption. Therefore, our data mining approach can help analysis to improve yield and quality of mass production with highly scaled devices.