The need for high-quality multi-media data increases the amount of data to be stored and processed, necessitating DDR5 to achieve high-density and high-speed with low-power consumption [1]. However, high-speed with low-power operation makes DRAM more vulnerable to process-voltage-temperature (PVT) variations, negative-bias thermal instability (NBTI), etc. In this work, a mono-die based 24-Gb high-density DDR5 achieving 6.4Gbps/pin is implemented. To lower power consumption, GIO switching is reduced by using a GIO separation switch and a read-only GIO pre-charge scheme. The proposed DRAM has a higher tolerance to NBTI, since the delay-locked loop (DLL) experiences slow toggling during self-refresh operations where the DLL is not necessary. Also, adaptive body bias (ABB) is used to combat process variation [2], thereby achieving high-performance I/O circuits. In addition, a low-pass filter is added for higher operations and sensitivities in front of charge pump, which is used by a duty cycle error detector (DCD) and a quadrature error detector (QED). Additionally, a balanced MUX and a bandwidth booster are also used in the transmitter for high-speed operations.

The need for high-quality multi-media data increases the amount of data to be stored and processed, necessitating DDR5 to achieve high-density and high-speed with low-power consumption [1]. However, high-speed with low-power operation makes DRAM more vulnerable to process-voltage-temperature (PVT) variations, negative-bias thermal instability (NBTI), etc. In this work, a mono-die based 24-Gb high-density DDR5 achieving 6.4Gbps/pin is implemented. To lower power consumption, GIO switching is reduced by using a GIO separation switch and a read-only GIO pre-charge scheme. The proposed DRAM has a higher tolerance to NBTI, since the delay-locked loop (DLL) experiences slow toggling during self-refresh operations where the DLL is not necessary. Also, adaptive body bias (ABB) is used to combat process variation [2], thereby achieving high-performance I/O circuits. In addition, a low-pass filter is added for higher operations and sensitivities in front of charge pump, which is used by a duty cycle error detector (DCD) and a quadrature error detector (QED). Additionally, a balanced MUX and a bandwidth booster are also used in the transmitter for high-speed operations.

This paper presents a reflection and crosstalk canceling continuous-time linear equalizer (CTLE) for high-speed DDR SDRAM interface. To enhance the voltage margin in noisy multi-drop DDR SDRAM channel, the proposed CTLE cancels reflection noise by common-mode compensation and compensates crosstalk by limiting RC filter charging to overcome inversion of common-mode information. The reflection and crosstalk canceling CTLE is implemented in a DRAM process and improves the average voltage margin of 16GB RDIMM at 3.2Gbps with 28.3mV.