Parallel-prefix adders draw significant amounts of attention within general-purpose and application-specific architectures because of their logarithmic delay and efficient implementation in VLSI. This paper proposes a scheme to enhance parallel-prefix adders for modulo 2(n) - 1 addition by incorporating Ling equations into parallel-prefix structures. As opposed to previous research, this work clarifies the use of Ling equations for Modulo and provides enhancements to its implementation. Results are given in this work for a placed and routed design within a variation-aware 45nm technology. The implementation results show a significant improvement in delay and even a reduction in power dissipation.

This paper discusses an extension to an open source, variation aware process design kit (PDK), based on scalable CMOS design rules. This PDK is designed for 45 nm feature sizes and is utilized for use in VLSI research, computer architecture, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit analysis. The kit also includes a standard cell library, MIPSreg processor and associated GNU-compliant compiler and the necessary support files to enable full chip place and route and verification for system on chip designs. An analog and digital system test chip is also included with this PDK-extension allowing exploration of nanometer-based VLSI designs.

Parallel prefix adders draw much attention because of their logarithmic delay. This paper proposes a scheme to enhance parallel prefix adders by incorporating the idea of carry-save addition within the prefix tree. Results are given for several designs using a publicly available nanometer library.