Memristive crossbar arrays enable in-memory computing by performing parallel analog computations directly within memory, making them well-suited for machine learning, neural networks, and neuromorphic systems. However, despite their advantages, non-volatile memristors are vulnerable to security threats (such as adversarial extraction of stored weights when the hardware is compromised. Protecting these weights is essential since they represent valuable intellectual property resulting from lengthy and costly training processes using large, often proprietary, datasets. As a solution we propose two security mechanisms: Keyed Permutor and Watermark Protection Columns; where both safeguard critical weights and establish verifiable ownership (even in cases of data leakage). Our approach integrates efficiently with existing memristive crossbar architectures without significant design modifications. Simulations across 45nm, 22nm, and 7nm CMOS nodes, using a realistic interconnect model and a large RF dataset, show that both mechanisms offer robust protection with under 10% overhead in area, delay and power. We also present initial experiments employing the widely known MNIST dataset; further highlighting the feasibility of securing memristive in-memory computing systems with minimal performance trade-offs.
Lightweight cryptographic designs are increasingly being deployed in energy-constrained environments such as the Internet of Things, where efficient hardware implementations are essential. Although recent small internal state stream ciphers like DIZY offer good performance in area and energy, their physical side-channel effects have not been fully established. In this work, we present a practical Correlation Power Analysis attack targeting the resynchronization phase of the DIZY-128 keystream generator. We demonstrate full internal state recovery using fewer than 4000 traces on an FPGA implementation. Our two-phase attack first identifies candidate values for each 5bit state word based on their correlation with power traces. It then reduces these to a single hypothesis for the entire state by correlating the implied next-round state values with the measured traces. These results show how design decisions made for energy efficiency and throughput can unintentionally expose exploitable leakage. Our findings contribute to the ongoing discussion on sustainable security architectures and we argue that secure lowpower hardware must be evaluated not only for efficiency but also for concrete resilience against implementation-level attacks.
Attention-based models demand flexible hardware to manage diverse kernels with varying arithmetic intensities and memory access patterns. Large clusters with shared L1 memory, a common architectural pattern, struggle to fully utilize their processing elements (PEs) when scaled up due to reduced throughput in the hierarchical PE-to-L1 intra-cluster interconnect. This paper presents Dynamic Allocation Scheme (DAS), a runtime programmable address remapping hardware unit coupled with a unified memory allocator, designed to minimize data access contention of PEs onto the multi-banked L1. We evaluated DAS on an aggressively scaled-up 1024-PE RISC-V cluster with Non-Uniform Memory Access (NUMA) PE-to-L1 interconnect to demonstrate its potential for improving data locality in large parallel machine learning workloads. For a Vision Transformer (ViT)-L/16 model, each encoder layer executes in 5.67 ms, achieving a 1.94x speedup over the fixed word-level interleaved baseline with 0.81 PE utilization. Implemented in 12nm FinFET technology, DAS incurs <0.1 % area overhead.
Many devices communicate externally in today's technologydriven world, creating cyber-attack vulnerabilities. To safeguard against these threats, utilizing an Intrusion Detection System (IDS) incorporating AI for effective anomaly detection is crucial. However, it is important to manage power consumption and latency carefully. Optimization of machine learning (ML) models can be achieved through three primary approaches: tuning hyperparameters and ML architecture via Neural Architecture Search (NAS) [1], enhancing existing ML architectures to improve robustness while reducing complexity [2], and optimizing for hardware implementation to strike a balance between Quality of Service (QoS) and Quality of Results (QoR) [3]. To address these challenges, we design a multi-level optimization approach that directly takes hardware and software constraints (such as QoS and QoR) into account during the optimization process with a hardware estimator (HE), greatly reducing the required number of actual ML architecture implementations. The main contributions are the fast exploration and evaluation of solutions based on a proposed hardware estimation regressor and the second is the ability to select and compare the most appropriate ML model architectures according to objectives and hardware constraints.
Many deep neural networks (DNNs) have been applied lately in the field of speech enhancement. One particular subfield, where DNNs have shifted the boundaries of what is considered possible, is noise reduction, where the degrading effects of sounds interfering with speech are minimized. This is especially relevant for hearing impaired listeners, as their ability to understand speech in noisy circumstances is reduced. In contrast to traditional methods, which are known to improve speech quality, DNNs promise to also improve speech intelligibility. Due to the high computational complexity, DNNs have not yet been deployed on a hearing aid processor, constrained by frequencies up to 50MHz and memory up to 2 MB. In this work we deploy a convolutional neural network (CNN) trained for noise reduction to a hearing-aid system-onchip (SoC) developed at our institute. Real time capability is achieved by thorough optimization of the C-Code, leading to a speed up by a factor of 88 for the inference relevant layers when compared to a naive C-Code implementation. The CNN approach is compared to an implementation of a traditional noise reduction method regarding their speech enhancement performance on white and complex noise and their computational cost. While both methods improve the speech quality measured with Perceptual Evaluation of Speech Quality (PESQ), only the CNN achieves a Short-Time Objective Intelligibility (STOI) improvement of 0.077 for complex noise. On the other hand, the CNN has a higher processor utilization of 60.1% compared to 23.5% for the traditional approach. Nonetheless, both methods are real time capable and consume only 3.3mW for the CNN and 1.78mW for the traditional approach, respectively.
Customizable processors—which allowed their instruction set architecture (ISA) to be augmented with applicationspecific custom instruction set extensions (ISEs)—arrived on the market at the turn of the millenium. Commercial offerings included the Tensilica Xtensa [1], ARC ARCtangent [2], STMicroelectronics ST200 [3] and MIPS with CorExtend [4]. Academic researchers developed compiler techniques to extract application-specific ISEs directly from high-level software source code, synthesize them in hardware, and integrate them into an extensible ISA. An early example of this work was a paper published by two of the authors in the Proceedings of the 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP) in 2003 [5]. This short retrospective looks back at some of the work of those years, reflects on why the topic all but disappeared from the research scene without producing any lasting industrial impact, and wonders about persisting threads of these efforts that may exist within the RISC-V ecosystem.
Transformer-based models have shown remarkable proficiency in extensive tasks for natural language processing, which are facing the ever-increasing need of processing long-context inputs. However, the memory footprint of the self-attention mechanism grows quadratically with the context length and becomes the bandwidth and memory bottleneck. Existing accelerators are mainly tailored for short sequences and struggle to handle attention in long-context scenarios. While some works attempt to mitigate this memory overhead with algorithmic optimizations, they suffer from limited hardware efficiency due to the sequential execution of backward-dependent iterations and additional computations. To this end, this paper proposes METAL, an algorithm-architecture co-optimized approach to support long-context inference with minimized memory overhead. First, we propose a hardware-friendly attention algorithm that eliminates the data dependency across inner loops, enabling full pipelining while keeping nonincreasing on-chip memory requirements, regardless of context length. Second, we develop a unified PE array for different dataflows across the transformer block to consistently support the entire inference with efficient data reuse. Moreover, an advanced non-linear operation module is designed to properly match the throughput of PE arrays with maximized resource sharing. Experimental results show that METAL on the Xilinx U200 FPGA outperforms other FPGA accelerators by 1.23 - 2.89x in normalized throughput and achieves up to 51.0% BRAM savings across different input sequence lengths.
Facing the challenge of increasingly sophisticated malware, it is imperative to develop an effective and adaptable malware detection framework. Hardware-level information has been shown to be very effective in detecting malware in the system through dynamic behavioral analysis at runtime. However, previous approaches suffer from the overhead of complex neural network models, as well as difficulty in scaling toward new attacks. In this work, we introduce a novel approach that leverages the Light Gradient-Boosting Machine (LightGBM) model, known for its efficiency and support for fast transfer learning method, to create a scalable and highly accurate malware detection system. Our framework achieves an exceptional detection accuracy of more than 99.90% for multiclass classification. Through transfer learning, the model can quickly adapt to new malware data and environments, significantly reducing the time and resources needed for retraining. Our results highlight the potential of using the LightGBM model to improve the malware detection framework.
Edge cloud computing is becoming increasingly vital to meet the computational demands of billions of interconnected devices, many of which operate under strict power and latency constraints. Modern 5G networks and advanced low-latency communication technologies enable rapid data transfer between edge devices and the cloud, making computational offloading both feasible and efficient. While traditional edge platforms have primarily relied on multi-core microprocessors, the growing architectural diversity of edge devices necessitates new approaches that support heterogeneous edge computing. This paper presents a novel edge computing framework that harnesses the capabilities of FPGAs to address the complexities of heterogeneous edge environments. A dynamically reconfigurable edge cloud enables seamless support for architecturally diverse edge devices. Central to our solution is an intelligent Offload Management System (OMS) that makes real-time decisions about whether to offload tasks or execute them locally, based on resource availability, energy efficiency, and deadline constraints. We validate our approach using an experimental setup featuring quad-core ARM Cortex-A76 and Qualcomm Snapdragon processors found in edge devices paired with an AMD ZCU104 FPGA board as an edge cloud node. Our results demonstrate how multiple edge devices can collaboratively utilize shared cloud resources via intelligent offloading. We specifically assess machine learning workloads processed with deep learning processing unit (DPU)-based models, showcasing the significant potential of a reconfigurable edge cloud in servicing edge devices.
Large language models (LLMs) are both storageintensive and computation-intensive, posing significant challenges when deployed on resource-constrained hardware. As linear layers in LLMs are mainly resource consuming parts and KV cache affects the deployment of LLMs, this paper develops a posttraining process for converting multi-head attention (MHA) into multi-head latent attention (MLA) and a tensor-train decomposition (TTD) for LLMs with a further hardware implementation on FPGA. The post-training MLA process reduces the KV cache by 25%. And TTD compression is applied to the linear layers in LLaMA2-7B models with compression ratios (CRs) for the whole network of 2.45x. The compressed LLMs are further implemented on FPGA hardware within a highly efficient group vector systolic array (GVSA) architecture, which has DSP-shared parallel vector PEs for TTD inference, as well as optimized data communication in this accelerator. Experimental results show that the corresponding TTD based LLM accelerator implemented on FPGA achieves a peak speed of 64.20 tokens/s and 1.54x reduction in first token delay for LLaMA2-7B models. Compared with NVIDIA A100 GPU, it achieves 46% higher throughput.
Design space exploration is essential for optimizing deep neural network accelerators, which face increasing computational and energy demands as model complexity grows. Previous approaches rely heavily on local insights, often neglecting the need for extensive exploration to improve the global perspective. This leads to challenges such as blind exploration and a higher likelihood of getting trapped in local optima. Without dynamic adjustments or adaptive strategies, these methods struggle to navigate large, complex design spaces effectively. In this paper, we propose PRDSE, a design space exploration framework based on reinforcement learning that integrates both intrinsic and extrinsic metrics, guided by prior knowledge. The proposed method incorporates an adaptive adjustment mechanism that dynamically balances intrinsic and extrinsic rewards based on the progress of exploration, improving both search efficiency and optimization performance. Compared to state-of-the-art methods, PRDSE achieves substantial improvements, with latency speedups of up to 3.49x in the cloud environment and 3.43x in the edge environment, respectively. This work demonstrates that PRDSE effectively balances exploration and optimization objectives, providing a more efficient and scalable approach to design space exploration in accelerator design.
High development complexity is one of the most critical issues preventing more widespread use of reconfigurable hardware accelerators such as FPGAs. While soft processor overlays allow productive development with high-level software tools, they suffer from low performance. We address this issue with Labidus, a parallel RISC-V soft processor overlay that addresses this performance gap while maintaining development simplicity. Labidus automatically generates custom instructions based on static analysis of user software. These custom instructions achieve high utilization through two key innovations: asynchronous semantics and sharing across four-core tiles. Our evaluation across four scientific computing applications shows that Labidus matches or exceeds the performance of even manually optimized FPGA accelerators for gigabyte-scale tasks, at a fraction of development effort.
State-of-the-art hardware countermeasures against fault attacks are based, among others, on control-flow and code integrity checking. Generalized Path Signature Analysis and Continuous Signature Monitoring can assert these integrity properties. However, many implementations of such mechanisms require a dedicated compiler flow and do not support indirect jumps, while others have prohibitive overheads. This work proposes a technique based on a ahead-of-time analysis to generate those signatures, associated with a hardware/software runtime handling indirect jumps while executing unmodified off-the-shelf RISC-V binaries. The proposed approach has been implemented on a pipelined processor, and experimental results show an average slowdown of x1.82 and an area overhead of at least x1.3 compared to unprotected implementations.
In recent years, Spiking Neural Networks (SNNs) have been increasingly deployed on Field Programmable Gate Arrays (FPGAs) for enabling low-energy AI inference. SNNs aim to enable more biomimetic processing than ANNs, thereby enabling more event-driven computing along with using cheaper arithmetic than multiply and accumulate operations. However, deploying large SNNs to achieve acceptable accuracy requires extensive use of configurable logic blocks (CLBs), leading to additional programmable routing and critical path delay. This study addresses these issues by exploring soft-logic architectures to reduce resource utilization for SNNs. We propose two architectures that provide a more efficient mapping of logic primitives for SNNs, reducing CLB usage by 13.49% and 20.13% compared to the Intel Stratix10 baseline. Implemented with an advanced technology node, these architectures achieve an average reduction of 8.30% and 7.30% in CLB area and reduce critical path delay by 2.72% and 3.42%, respectively, enabling larger SNNs with faster inference within the same programmable fabric.
Efficient and secure hardware implementations of post-quantum cryptographic schemes are critical for real-world adoption. In this work, we propose a unified FPGA-based architecture for Kyber and Dilithium that combines flexibility, lightweight design, and fault tolerance. The architecture adopts a microcoded, programmable datapath supporting both schemes with minimal area overhead, enabling seamless integration of modules such as SHAKE, sampling, and coefficient rounding. To enhance resilience against propagation-based fault attacks-which exploit effective/ineffective fault behavior in public-domain computations-we embed a probabilistic verification mechanism using rejection sampling. This countermeasure transforms deterministic operations into cryptographically constrained probabilistic processes that remain efficient under normal conditions while significantly degrading under adversarial faults. The result is a robust and compact design that not only supports both a lattice-based KEM and signature scheme, but also provides the first unified fault countermeasure architecture for Kyber and Dilithium, maintaining low retry counts and minimal performance degradation in fault-free environments.
The Higher Order Table-Based Method (HOTBM) was published [1] during Jeremie Detrey's PhD. It was at the time one of the most advanced generic methods for fixed-point hardware function evaluation. This article reviews its legacy, some of the subsequent progress in this field, and the challenges that remain.
dWith Deep Learning dominating modern applications, area-efficient and simultaneously high through-put acceleration of inference has become a crucial application. Constant Matrix Vector Multiplication (CMVM) dominates the computational complexity of these workloads, and its efficient acceleration is essential. Our proposed architecture introduces a groundbreaking extension to Computation Coding for dataflow architectures, achieving a 2.3x performance boost for small matrices and paving the way for more efficient Deep Learning inference at a performance of up to 93.52 GOP s using a single core.
dDeploying real-time intelligent systems at the edge poses significant challenges in dynamic, resource-constrained, and low-visibility environments. We present a bio-inspired event camera architecture for robust and adaptable continuous target detection and tracking under tough environmental conditions. Leveraging the high temporal resolution and dynamic range of event-based sensing, our approach addresses key limitations in small object detection and low-light imaging. Built on HARP (Hierarchical Attention-Oriented Region-Based Processing [16]), our hardware platform prioritizes salient regions and performs early-stage, sensor-level information extraction. This attentionguided strategy reduces redundant spatiotemporal processing and enables learning models to focus computation on critical regions. A hierarchical and parallel pipeline further maximizes throughput by exploiting high-bandwidth image access. We prototyped the system on FPGA and validated its performance in two key tasks: small object detection and low-light enhancement. Compared to prior FPGA-based designs, our system reduces logic resource usage by up to 88%, increases throughput by 47%, and lowers latency by over 30%. For enhancement, it achieves 14% lower MSE, 4.5% higher PSNR, and 7.1% higher SSIM. Our quantized detector maintains strong semantic accuracy with only 7.05% degradation from its float baseline, using just 1.1M MACs and 42K parameters-suitable for real-time deployment on embedded platforms.
dQuantization of weights and activations in neural networks is widely used to reduce data movement and the computational footprint of multipliers in arithmetic units. However, this increases the relative area contribution of adders. Most recent work in neural network quantization uses large floating-point accumulators due the large rounding and clipping errors incurred by smaller accumulators even if weights and activations are otherwise quantized to narrow data types. In this work, we propose a novel method of finding and applying permutations to weight and activation order in neural networks to reduce the error induced by small floating-point adders for the multiply accumulate (MAC) functions in matrix multiplications. Our method optimizes the order of accumulation with very low computational overhead by using a shared ideal order for a group of vectors instead of an ideal order for each vector, and using a static order rather than dynamically generating one at runtime. Our technique does not require quantization-aware training (QAT) or modification of weights, making it applicable to large language models (LLMs).
Graph Neural Networks (GNNs) have demonstrated exceptional performance in real-world applications, which often involve large-scale graphs with billions of vertices and numerous features per vertex. Large-scale workload requires multi-node systems to enhance computing power and memory capacity. However, accelerating large-scale GNNs on multi-node systems faces two key challenges. (1) Graph irregularity and high-dimensional features lead to excessive redundant inter-node communication. (2) Computational dependency in GNN results in waiting issues and underutilization of computing resources in accelerator nodes. To address the challenges, this work proposes PAMA, a preaggregation-based multi-node architecture for GNN acceleration. For challenge (1), we propose a pre-aggregation approach to avoid redundant feature transmissions, which is facilitated by a complementary communication scheme. For challenge (2), a batched staggered aggregation-transformation pipeline dataflow is proposed to alleviate the waiting issues. Additionally, a reconfigurable computing core that dynamically adapts to different workloads is designed to further improve computing resource utilization. The evaluation results show that PAMA achieves a 9.5-16x speedup over the baseline multi-node system.
