Junction engineering solutions are presented in this work to improve the triggering and performance of SCR devices in an advanced 22nm SOI CMOS technology. Several SCR cathode junction formations are investigated including implants energy, dosage, with or without halo/extension implants. TLP and HBM results are presented in details.

We present ESD device results from a 14nm FinFET SOI CMOS technology. Both fin-based and planar-based approaches are evaluated, with the planar-based diode design achieving 7 times higher failure current per silicon area. Planar-based diodes also show 25% higher failure current when Tsi increases by 40%.