In the three decades of production, SiGe HBTs have numerous applications including RF and high-speed mixed-signal and analog. While successive generations of BiCMOS technologies in the past have employed process and layout scaling, the advanced high performance platforms (with several 100 GHz fmax) have mostly been restricted to SiGe NPN optimization, and the Si PNP is often only offered as a dependent device with significantly slower speed. There truly exists a gap in literature with the PNP device variants showcasing good fT and fmax above 150 GHz in a BiCMOS platform. It is worth noting that much of the serviceable applications above can be designed with NPN-only topologies. However, having the complementary PNP enables several advantages, including power savings, improved gain, reduced design complexity, and improved reliability. There are several challenges for making high performance PNP devices including reduced minority mobility in the intrinsic base from the conducting holes, elevated base current from minority electron injection into the emitter, and heterojunction barrier effect directly on the carrier pathway in the collector-base junction. The figure below shows the measured fT/fmax characteristics for a SiGe PNP with Ae = 0.12x2.5 um2 built using a 130nm technology framework optimized for a PNP-only process. The present work expands on the measured results (AC + DC) and the challenges faced in optimizing PNP performance for 200 GHz fmax and beyond. Figure 1

High Performance (HP) SiGe HBTs integrated in a 45nm PDSOI BiCMOS process with peak $f_{T}/f_{MAX}415/610$ GHz are reported here. These are the highest f MAX silicon devices demonstrated in any SOI platform. Measured $f_{T}/f_{MAX}$ at transmission line metal level for this HBT is 388/600GHz which gives significant performance benefit over CMOS in RF circuit designs. HBTs are integrated in a hybrid region on the wafer formed by removing the SOI and BOX with an epitaxial growth and planarization to form a co-planar top surface with the SOI. In addition to the HP HBTs and CMOS, the process also integrates a medium breakdown HBT with $f_{T}/BV_{CBO} =270$ GHz/5.6V and RF N/P FETs with $f_{T}/f_{MAX} =270/355$ GHz and 240/295 GHz. An early CML RO design has a gate delay of 1.76ps. Simple cascode power cells show > 23 dB gain at 70GHz and > 18 dB gain at 100GHz.

Gallium Nitride is of interest due to its direct bandgap, which allows for efficient emission in the near-UV range. Bulk GaN is already in use in solid-state devices that exploit its emissive properties, however, the promise of GaN nanocrystals as tunable emitters for use in light-emitting devices and lasers has led to the recent exploration of nanocrystalline GaN synthesis routes. Here we discuss the use of nonthermal plasmas for the synthesis of nanocrystalline pow-ders of GaN. The particles were examined using transmission electron microscopy and x-ray photoelectron spectroscopy.

The decarbonylation of 2-pyridyl-substituted ketones via transition metal-catalyzed carbon–carbon bond activation provides ready access to a variety of biaryl compounds. The highly efficient and general method provides reliable decarbonylation of benzophenones including a range of functional groups and substitution patterns. The methodology has also proven highly efficient for heteroaromatic substrates, including those containing thiophenyl, indolyl, quinolinyl, and pyridine substitution.

A 45nm BiCMOS process, based on PDSOI CMOS, with SiGe HBT NPNs having ${f_{T}f_{\max}\,=\,375/510GHz}$ is presented. The bipolars are integrated on a PDSOI wafer in an epitaxial region above the handle wafer to avoid self-heating concerns. To our knowledge, this is the first time a high performance SiGe BiCMOS process has been demonstrated on a PDSOI wafer. In addition to the HBTs, the technology features high performance NFETs with ${f_{T}f_{MAX}\,=\,265/330GHz}$ and PFETs with ${f_{T}f_{MAX}\,=\,250/340GHz}$ enabling flexibility in circuit design. A full-flow demonstration PDK, digital standard cell and IO cell libraries have been released for experimental circuit design work. This work, funded under the DARPA T-MUSIC program, will address future extensions to higher HBT performance and more-advanced CMOS nodes.

The decarbonylative coupling of phthalimides with aryl boronic acids provides ready access to a broad range of ortho-substituted benzamides. This nickel-mediated methodology extends reactivity from previously described air-sensitive diorganozinc reagents of limited availability to easily handled and widely commercially available boronic acids. The decarbonylative coupling is tolerant of a broad range of functional groups and demonstrates little sensitivity to steric factors on either of the coupling partners.

Process sensitivity and variation, such as layer thicknesses, etch dimensions and doping levels are all process parameters that should be well understood when assessing their impact on end of process wafer quality and device performance. Improvements in uniformity of electrical device performance is often not taken into major consideration until a certain maturity level of a technology is reached. In this work, use of technology computer aided design (TCAD) and process compact models (PCM) developed from neural networks demonstrate their utility in process- parameter variation understanding in earlier stages of technology development. A TCAD simulation was built and calibrated to match key electrical performance metrics of an experimental high performance SiGe HBT in 130nm BiCMOS technology, which was the device of focus in this study. Figure 1 includes a TCAD cross section of the device1. Neural net techniques, a machine-learning methodology, the development and deployment of which has grown significantly over the last three decades, is used to expand the scope of TCAD to process variability2-3.The aforementioned calibrated TCAD deck was used to generate training data for the neural network process compact model in place of hardware data. Key process features, as listed in table 1 were a few of the process conditions that were varied from nominal values to characterize the variation in resulting electrical performance. Figure 2 includes a 1D schematic view of the epitaxial layers of the HBT, highlighting some of the process features varied in simulation. The neural network was trained using a data analysis suite using three hidden layers with 16 neurons each to get a best fit to the training data input and output values. The foundation of this approach was a TCAD simulation calibrated to match performance of the nominal HBT device of focus. Key AC and Gummel performance parameters had good agreement with hardware data as illustrated in Figure 3a and b. Thousands of individual TCAD simulations with combinations of varied process feature values were then executed to generate neural network training data in lieu of hardware data- utilizing reported standard deviations of each process parameter. The trends and sensitivity of this data was then reflected in the process compact model, which would provide results for large-scale calculation and analysis. Beta was the electrical parameter of focus in this study, where its changes in process variation (mean and standard deviation) were predicted by the trained PCM. The agreement with hardware electrical parameter Beta with respect to Boron dose in Figure 4 demonstrates how use of calibrated TCAD as a basis can empower prediction of large-scale hardware results without the extent of hardware expense. Use of this tool can be extended to simulate and analyze larger populations than what would be feasible for hardware (in several thousands) to predict the effect of process input changes on uniformity of electrical parameters. Figure 5 demonstrates how the changes in standard deviation of Beta can be predicted as a function of Boron dose variation-through generation of large simulated populations by the PCM. The resulting work on a state-of-the-art SiGe BiCMOS technology demonstrates how specific simulation tools, like TCAD-trained process compact models can be leveraged for enhanced process understanding and improvement. The data generated from these tools can supplement or replace hardware and corresponding data, saving in development costs and associated hours in manpower. They can also enable earlier and more agile decision-making about key production metrics throughout the technology development process. Calibrated TCAD infrastructure, coupled with neural-net technology have potential to fulfill pivotal roles through the timelines of technology development, rather than just being utilized when a technology is mature. References: J. Pekarik et al., "A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications," 2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Coronado, CA, 2014, pp. 92-95. W. Coit, B.T. Jackson & A.E. Smith, “Static neural network process models: Considerations and case studies,” International Journal of Production Research, 1998, 36:11, pp. 2953-2967. Borges, T. Ma, W. Ng, S. Krishnamurthy and L. Bomholt, "Implementation of TCAD-for-Manufacturing Methodology using Process Compact Models," 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai, 2006, pp. 1853-1856. Figure 1

This paper presents a systematic methodology by thermal characterization and simulation of a 3-FET stacked K/Ka-band class-AB power amplifier built on GLOBALFOUNDRIES 45nm SOI process. A detailed temperature profile is obtained in the FEOL and BEOL stacks by first using special gate Kelvin measurement structures and novel Kelvin metal sensor stack at several Mx layers (M 1 -M 5 ), which calibrate models to then be applied in a thermal simulation of the PA itself.

Impact of process choices in terms of work function (WF) tuning and junction implant energy optimization for hot carrier (HCI) reliability in advanced FINFET technology is discussed here. The work focuses on understanding the nature and location of defects generated under different process conditions. Experimental observations are confirmed here with TCAD based simulations. For the first time, it is observed that maximum substrate current increases as stress progresses in contrast to traditional HCI mechanisms. To reduce HCI degradation, in addition to junction optimization, an additional knob is available in scaled FETs is the WF optimization, which can provide significant HCI reliability relief.

We present a fully integrated 7nm CMOS platform featuring a 3 rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um 2 . This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.

Utilizing rhodium catalysis, aryl nucleophiles generated via carbon-carbon single bond activation successfully undergo oxidative coupling with Michael acceptors. The reaction scope encompasses a broad range of nucleophiles generated from quinolinyl ketones as well as a series of electron deficient terminal alkenes, illustrating the broad potential of intersecting carbon-carbon bond activation with synthetically useful coupling methodologies. The demonstrated oxidative coupling produces a range of cinnamyl derivatives, several of which are challenging to prepare via conventional routes.

Performance enhancement is critical for offering competitive CMOS solutions for advanced technology nodes. To fully leverage performance enhancement elements the device reliability impact needs to be comprehended on the CMOS circuits like SRAM and ring-oscillators. We reaffirm that time-zero and BTI induced stochastic variation are most critical for SRAM circuits while for logic circuits such as ring-oscillators the focus is on the mean degradation. In addition we explore the impact of self-heating on the correlation of device to circuit degradation for the FinFET device architecture.

Historically, the primary objective of cotton (Gossypium hirsutum L.) breeding programs was to improve the quantity and quality of cotton fiber. Because of the added value of cottonseed and its many uses, including a feed and human food source, there is interest in developing cotton breeding programs that focus improvement efforts simultaneously on cotton fiber and seed. Genetic analysis of cottonseed traits, such as protein and oil, is a prerequisite to building new joint fiber and seed cotton breeding programs. In this study, we conducted a genetic analysis of a diverse set of elite upland cotton germplasm for cottonseed protein and oil. Environment was responsible for a sizeable portion of the total variation for protein and oil, and genetics accounted for a larger portion of variation for oil than protein. Genotype × environment (G × E) interactions significantly impacted oil but not protein. Genotypic correlation analysis found a strong, negative relationship between protein and oil. Positive genotypic correlations were found for protein and several agronomic traits including lint yield; whereas, negative correlations were found between oil and lint yield along with other agronomic traits. Overall, results showed very little association between protein, oil, and fiber quality traits. These findings indicate that altering protein and oil seed composition will impact yield and yield component traits. However, alterations in seed composition should not impact fiber quality.

A rhodium-catalyzed cross-coupling of aryl and aliphatic quinolinyl ketones with boronic acids has been developed. Proceeding via quinoline-directed carbon-carbon σ bond activation, the transformation demonstrates tolerance of a range of functional groups on both the ketone and aryl boronic acid substrates, providing good to excellent yields of the new ketones, particularly those containing electron-withdrawing substituents. Catalyst reactivity is dependent on quinolinyl ketone substrates, with alkyl ketones requiring Rh(PPh3)3Cl instead of the more reactive [Rh(C2H4)2Cl]2. With the use of K2CO3 as an additive, methyl boronic acid is also a competent substrate, giving rise to an unprecedented methylation technique.

The decarbonylative coupling of phthalimides with diorganozinc reagents to form o-substituted benzamides has been previously demonstrated as a viable process, but only with stoichiometric nickel(0). Investigations into a number of reaction variables, including solvent, ligand, and substrate substitution, have yielded multiple sets of conditions capable of achieving up to 10 catalyst turnovers, most successfully with the use of electron withdrawing nitrogen substituents on the phthalimide. In addition, these investigations have provided insight into the intermediates within the catalytic cycle and have revealed new approaches to the development of a general catalytic methodology. (C) 2016 Elsevier Ltd. All rights reserved.

Using a finite element based treatment, the Schrödinger equation is solved in 3D for non-planer devices like FinFETs. Discrete states appearing because of three dimensional geometric and electrostatic confinement in a FinFET are used to calculate the quantum mechanical charge which is solved self-consistently with the Poisson equation in FIELDAY. A hybrid approach is used in which the Schrödinger solver is active in a smaller region and continuum models are used in the remaining simulation domain. The domain is chosen such that it is possible to match the quantum charge and the continuum charge. The methodology and results from this Schrödinger–Poisson solver are presented here and the need to include these effects is highlighted.

We explore the use of oxygen vacancies for nonvolatile data storage by trapping electrons in the high-k, gate dielectric layer of NFETs. Programming is performed via channel carrier injection and is erased by tunneling. 64Kb arrays were constructed and reliability is demonstrated.