The low-impedance contact CDM (LICCDM) ESD tester can be used for wafer-level CDM testing. However, compared to the industry standard field-induced CDM (FI-CDM), it shows some differences. We investigate solutions to mitigate these differences which are mainly the wafer chuck influence and the probe reflections due to matching.

We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.

Latchup sensitivity is often measured with a single, collinear PNPN test victim. This method is insufficient for measuring the latchup performance of advanced CMOS technology because it does not represent real-world designs. As a result, the predicted latchup performance is too optimistic. In this work, more realistic latchup test structures are discussed. By adopting these new structures, a more accurate prediction of product-level latchup sensitivity can be measured with test structures, enabling more optimized designs with fewer design revisions.

Latchup sensitivity is often measured with a single, collinear PNPN test victim. This method is insufficient for measuring the latchup performance of advanced CMOS technology because it does not represent real-world designs. As a result, the predicted latchup performance is too optimistic. In this work, more realistic latchup test structures arc discussed. By adopting these new structures, a more accurate prediction of product-level latchup sensitivity can be measured with test structures, enabling more optimized designs with fewer design revisions.

The 16.6 ohm implementation of contact CDM (LICCDM) recently published in ANSI-ESD Standard Practice 5.3.3 is shown to produce waveforms of similar shape, I fail , and I peak vs. C eff dependency as JS-002. The non-monotonicity of JS-002 at low voltages is overcome using LICCDM. A path to joint standardization with air discharge testing is proposed.

Standard charged device model (CDM) ESD simulators used today cannot be used at wafer level and suffer from high zap-to-zap peak current variability at low voltages. The low-impedance contact CDM provides a solution to these problems. In this paper we evaluate its performance and propose a model for the setup.

A scalable I-V model for latch-up in non-collinear PNPN devices is adapted from a previous model for collinear SCR devices. The model is applied to 14-nm FinFET test structures. Layout scaling trends for key latch-up metrics, such as holding and trigger voltage, are captured by the model in circuit simulation. TCAD simulation is used to gain physical insight into the behavior of non-collinear PNPN devices.

Relay-based contact CDM (CCDM) is shown to closely replicate the waveforms and failure currents of legacy field-induced CDM when the effective system impedances are approximately matched. The repeatability of the waveforms will be crucially important as CDM test levels decrease below 250 V. Recommendations for inclusion in future standards are presented.

Two-pole RLC models, matching peak current and charge under the first current peak, are shown to fit CDM waveforms well, as they target features that cause device failure. RLC properties of ferrites, air sparks, varying dielectric and other tester elements become clear and point us to a revised CDM test standard.

-vTLP/HBM/MM/CDM Device Testing: Testers, Methods, and Correlation Issues Sub-Committee Chair: Theo Smedes, NXP Semiconductors Robert Ashton, ON Semiconductor Evan Grund, Grund Technical Solutions, LLC Marty Johnson, Texas Instruments, 1m: David J ohnsson, High Power Pulse Instruments GmbH Tom Meuse, Thermo Fisher S cientijic Masanori Sawada, HANW A Electronics Wolfgang Stadler, Intel Mobile Communications

A bidirectional SSTL I/O which utilizes an active-biasing technique to achieve enhanced ESD resilience is presented. During an ESD event, each vulnerable transistor has an appropriate bias applied to minimize the peak voltage across gate oxide and drain-source regions. Active-bias control circuits can be substituted for secondary protection to improve circuit performance and ESD reliability.

The on-chip stresses induced by FICDM, WCDM2, CC-TLP, and VF-TLP are compared on the basis of voltage monitor readings and IC functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics increase the FICDM current rise-time at an I/O pad relative to that measured externally, causing miscorrelation with wafer-level testers.

A new ESD testing system, the exponential-edge transmission line pulse system (EETLP), is presented. EETLP generates 100ns square pulses with a variable, exponentially decaying falling edge. When applied to an ESD protection device, the pulse shape allows for capture of both the transient and quasi-steady-state responses, in the context of a single measurement. EETLP provides unprecedented insight into the turn-off dynamics of snapback-type devices. Device measurement data are presented to demonstrate the capabilities of EETLP.

CDM-ESD robustness of stacked-die packages is investigated and compared with single-die packages. The peak discharge current is not increased significantly by die stacking. The inter-die signal interfaces are shown to be well protected against CDM by placing just a small ESD protection clamp at the receiver, if certain package integration guidelines are followed.

CDM-like unipolar pulses are generated at the wafer level with excellent repeatability and linearity. Pulse width and rise time resemble that of FICDM testers. In-situ pre- and post-stress curve tracing reveals the current failure threshold for the device under test.

Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.