In this paper, we propose the design of a generic security interface for RISC-V. This interface increases flexibility of security modules by creating an environment that can operate independently on a host processor. We also present an application using this interface for the memory protection. To check the feasibility of our idea, we implement an early prototype where a RISC-V processor is connected with the proposed hardware components using our interface. The empirical results show that our security interface has enabled a security module operated independently of the processor with no performance and low area overhead.

Large OS kernels always suffer from attacks due to their numerous inherent vulnerabilities. To protect the kernel, hypervisors have been employed by many security solutions. However, relying on a hypervisor has a detrimental impact on the system performance due mainly to nested paging. In this paper, we present Hypernel, a security framework combining hardware and software components to address this problem. Hypersec, the software component, provides an isolated execution environment for security solutions, and the hardware monitor component enables a word-granularity monitoring capability on the kernel memory. Our evaluation shows that Hypernel efficiently fulfills the role of a security framework, while imposing mere 3.1% of runtime overhead on the system.

Intrinsic drain current-gate voltage characteristics (I-D-V-GS) of the WSe2 field effect transistors (FETs) are obtained by adopting single channel pulsed I-V (PIV) measurement. In the transfer curves measured by a typical DC method, the hysteresis is large and affected by a gate bias (V-GS) sweeping range. In addition, the threshold voltage (V-th) shift is observed as a drain bias (V-DS) increases. By adopting the single channel PIV measurement with a short on time (t(on), similar to 10(-4) s), a long off time (t(off), similar to 1 s), and a base voltage (V-base, V-GS during t(off)) of 0 V, the hysteresis-free I-D-V-GS curves are demonstrated regardless of the V-GS sweeping range. Furthermore, we also show that the V-th shift is negligible in the transfer curves measured by the single channel PIV with the V-base of the half of the V-DS, which makes V-GS stress during t(off) identical to the average channel potential. With elimination of the V-GS and V-DS stress, we demonstrated the intrinsic transfer characteristics of the WSe2 FETs showing ignorable hysteresis without V-th shift and remarkably enhanced mobility and conductance.

A novel poly-Si reconfigurable device with a programmable bottom-gate (BG) array is demonstrated for the first time. The BG has non-volatile memory functionality. This device is very efficient in terms of device size and functionality. By changing the bias or program/erase state of the BGs, a device can be transformed to a certain device type among n-/p-MOSFETs, and n-p and p-n diodes. The threshold voltage (V-th) and contact resistance (R-c) of MOSFETs can be controlled independently by the BGs. The subthreshold swings for n-/p-MOSFETs are 200 and 230 mV/decade, respectively. The I-ON/I-OFF s of the n-/p-MOSFETs measured from a single reconfigurable device are more than 106, which are comparable to those of conventional poly-Si devices.

Intrinsic transfer and output characteristics of WSe2 field effect transistors are obtained by adopting the dual channel pulsed I–V measurement. Due to the DC gate bias stress during the measurement, a large hysteresis is observed and increased with increasing the sweeping range of the gate bias in the transfer curves. In addition, as a drain bias increases, the drain bias stress during the measurement induces the threshold voltage shift. The output curves measured by a DC method are significantly affected by the drain bias sweeping direction and the previous measurement, which leads to a large error in the analysis. By using the dual channel pulsed I–V measurement with a short turn-on time (10−4 s), a long turn-off time (1 s), and a base voltage (gate and drain bias during turn-off time) of 0 V, hysteretic behaviors caused by the gate bias stress and threshold voltage shift due to the drain bias stress in transfer curves are eliminated. The effect of the drain bias sweeping direction and the previous measurement in output curves are also eliminated, and the output curves show a typical field effect behavior. The intrinsic characteristics of WSe2 field effect transistors show negligible hysteresis and remarkably enhanced mobility (∼200 cm2/V s), and higher current drive capability compared to those of DC measurements.

Transfer characteristics of the WSe 2 field effect transistors are measured by the dc, fast I-V, and pulsed I-V methods. In the dc measurement, large hysteresis is observed. In the fast I-V measurement, less hysteresis is obtained with a faster sweeping rate, however, the hysteresis is still not negligible. By applying the pulsed I-V method with short on time (~10 -4 s), and long off time (~1 s), the hysteresis-free characteristics of WSe 2 FETs are obtained, and noticeably enhanced mobility (~160 cm 2 /V·s) is observed.

The cause of drain current (I-D) drift in graphene field-effect transistors is analyzed and a method to suppress the drift is proposed. By analyzing I-D-time characteristics, a condition of reasonable gate, drain and source biases (V-G, V-D, and V-S) is proposed to suppress I-D drift. Based on this result, we find a condition for V-G during off-time (V-base), V-D, and V-S in pulsed I-V measurement to obtain the intrinsic I-D-V-G curves, and analyze the effect of V-base on the Dirac point shift. Through an analysis of I-D-time characteristics depending on V-G, I-D drift according to the range of V-G is explained.

We investigated drain current-gate voltage (ID-VG) and ID-time (t) characteristics in electrolyte-gated graphene field effect transistors (GFETs). The counterclockwise hysteresis appearing in ID-VG curves with fast sweeping rate is caused by the displacement current, and thus limits the operating speed of electrolyte-gated GFETs. By analyzing the ID-t characteristics of electrolyte-gated GFETs having different areas of the overlap between the gate and the source/drain electrodes, the effect of the parasitic capacitance (Cpara) on the displacement current is demonstrated. The characteristics of GFETs with metal gate are also reported to verify the effect of the Cpara.

An Ion Field Effect Transistor (IFET) with nanopore structure was modeled in a conventional 3-dimensional (3-D) device simulator to understand current-voltage (I-V) characteristics and underlying physics of the device. Since the nanopore was filled with positive ions (K+) ions due to the negative interface charge on the insulator surface and negative gate bias condition, we could successfully simulate the IFET structure using modified p-type silicon to mimic KCl solution. We used p-type silicon with a doping concentration of 6.022 x 10(16) cm(-3) which has the same concentration of positive carriers (hole) as in 10(-4) M KCl. By controlling gate electric field effect on the mobility, the I-V curves obtained by the parameter modeling matched very well with the measured data. In addition, the decrease of [V(th)] with increasing V(DS) was physically analyzed.

Current-voltage (I-V) characteristics of the graphene field effect transistors (GFETs) are measured by the dc, fast I-V (FIV), and pulsed I-V (PIV) methods and analyzed. The hysteresis and conductance in the dc measurement are affected by the sweeping bias range and direction. The I-V curves measured by the FIV method show reduced hysteresis and enhanced conductance at a faster sweeping rate, but are still affected by the sweeping bias range. By applying the PIV method, the hysteresis can be suppressed significantly while the conductance is improved by controlling turn-on, turn-off times (t(on) and t(off)) and the gate bias during t(off) (V-base) regardless of the sweeping bias range. With short t(on), long t(off), and V-base of 0 V, the hysteresis-free characteristics of GFETs are obtained.

A high-performance amorphous indium-gallium-zinc-oxide thin-film transistor (TFT) inverter, which is composed of an enhancement mode driver and a depletion mode load, is implemented by selectively inducing the negative bias illumination temperature stress (NBITS) to the load TFT. Under NBITS, the transfer curve of the load TFT shows a parallel shift into the negative bias direction without a significant change in the subthreshold slope and recovers very slowly after terminating the NBITS even under harsh bias and temperature stress conditions. The proposed inverter shows much improved switching characteristics including higher voltage gain, wider swing range, and higher noise margins compared to the conventional inverter with an enhancement load.

In this paper, we propose a method for simulating nanopore structure by using conventional 3-D simulation tool to mimic the I-V behavior of the nanopore structure. In the simulation, we use lightly doped silicon for ionic solution where some parameters like electron affinity and dielectric constant are fitted to consider the ionic solution. By using this method, we can simulate the I-V behavior of nanopore structure depending on the location and the size of the sphere shaped silicon oxide which is considered to be an indicator of a DNA base. In addition, we simulate an Ionic Field Effect Transistor (IFET) which has basically the nanopore structure, and show that the simulated curves follow sufficiently the I-V behavior of the measurement data. Therefore, we think it is reasonable to apply parameter modeling mentioned above to simulate nanopore structure. The key idea is to modify electron affinity of silicon which is used to mimic the KCl solution to avoid band bending and depletion inside the nanopore. We could efficiently utilize conventional 3-D simulation tool to simulate the I-V behavior of nanopore structures.