Fuzz testing is a widely used technique to detect software defects and vulnerabilities. Coverage-guided fuzzing aims to improve code coverage by generating offspring test cases through mutation, executing the program under test, and retaining interesting seeds for subsequent mutations using customized genetic algorithms. However, existing fuzzing tools rarely consider the similarity between seeds during mutation. Mutating similar seeds frequently generates similar offspring test cases, which results in similar coverage and reduces the efficiency of fuzz testing. To alleviate the impact of this problem on fuzz testing, this paper proposes a fuzz testing method based on seed diversity analysis, which focuses on the characteristics of seeds and uses byte sequences as a feature to measure the similarity between seeds. It collects seeds that can cover new edges and constructs a shorter seed queue with significant differences based on this feature, which replaces the original seed queue for mutation. Based on the proposed method, we implement the prototype tools AFL-Varied and Neuzz-Varied. Compared with AFL and Neuzz on six projects, the edge coverage and basic block coverage can be increased by 214.57% and 233.33 % at most, respectively.

Symbolic execution is a powerful technology in ensuring software correctness. However, symbolic execution has the path explosion problem and cannot scale to large programs. In this paper, we present a novel approach, hotness-guided symbolic execution which uses hotness as a strategy to find bugs, and implement it on a bug finding tool HOE. Based on our observation of real world bugs, most bugs are caused by programmers' careless dealing with unexpected situations. HOE chooses these not-so-often-reached paths to explore in a high priority and ignore hotter paths on demand. We evaluate HOE on an open source C++ library oSIP with 7.9k lines of code and a TTCN-3 distributed testing platform Loong Testing with 94.5k lines of code. The results show that our approach is efficient and can find bugs faster, and thus useful when testing large programs.

With the popularity of embedded systems, low power design has become one of the most challenging tasks in embedded systems development. This paper presents a novel method to reduce the power consumption of an embedded system by register re-assignment. Register re-assignment is based on statistics concerning register adjacency collected through instruction level simulation. It is illustrated that this method is an effective way to reduce the power consumption of embedded systems.

Using ASIP in an embedded system can achieve the balance among design cycle, performance, power consumption and flexibility. Considering the features of embedded applications and ASIP, this paper proposes a low power ASIP architecture, in which a special instruction is merged into the ISA and a loop handling unit is incorporated into pipeline structure. The results of our experiment show that this architecture is effective. To some application, about 40% reduction in power is achieved.

ASIPs are designed specifically for a particular application or a set of applications. Their instruction sets must be carefully tailored to provide high performance as well as to meet non-functional constraints such as silicon area and power consumption. Traditionally, evaluation of different candidate instruction sets is all carried out through simulation. However, the growing design complexity and time-to-market pressure have rendered simulation increasingly infeasible. In this paper, we present an instruction level modeling method that can rapidly evaluates several important aspects of a selected instruction set. Experimental results show that we can prune a large number of candidate instruction sets with the model, accelerate design space exploration and alleviate the pressure on simulation

Various applications and the time-to-market of the embedded system pose new challenges to the ASIP architecture design.An ASIP design framework,A~2IDE(ASIP architecture integrated design space exploration environment) is proposed,which divides system-level design into three levels,including ISA,pipeline,and microarchitecture.It adopts architecture description language(ADL) and automatically generated toolkit to conduct design space exploration.The characteristics and framework of the A~2IDE are introduced.The experimental results preliminarily show that the framework is effective.