Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized hardware designs and, when used effectively, can make hardware descriptions shorter, more understandable, and more reusable. In practice, however, designers avoid these constructs because it is difficult to understand and predict the properties of the generated code. Is the generated code even type safe? Is it synthesizable? What physical resources (e.g. combinatorial gates and flip-flops) does it require? It is often impossible to answer these questions without first generating the fully-expanded code. In the Verilog and VHDL communities, this generation process is referred to as elaboration. This paper proposes a disciplined approach to elaboration in Verilog. By viewing Verilog as a statically typed two-level language, we are able to reflect the distinction between values that are known at elaboration time and values that are part of the circuit computation. This distinction is crucial for determining whether abstractions such as iteration and module parameters are used in a synthesizable manner. To illustrate this idea, we develop a core calculus for Verilog that we call Featherweight Verilog (FV) and an associated static type system. We formally define a preprocessing step analogous to the elaboration phase of Verilog, and the kinds of errors that can occur during this phase. Finally, we show that a well-typed design cannot cause preprocessing errors, and that the result of its expansion is always a synthesizable circuit.

Cyber-physical systems comprise digital components that directly interact with a physical environment. Specifying the behavior desired of such systems requires analytical modeling of physical phenomena. Similarly, testing them requires simulation of continuous systems. While numerous tools support later stages of developing simulation codes, there is still a large gap between analytical modeling and building running simulators. This gap significantly impedes the ability of scientists and engineers to develop novel cyber-physical systems. We propose bridging this gap by automating the mapping from analytical models to simulation codes. Focusing on mechanical systems as an important class of physical systems, we study the form of analytical models that arise in this domain, along with the process by which domain experts map them to executable codes. We show that the key steps needed to automate this mapping are 1) a light-weight analysis to partially direct equations, 2) a binding-time analysis, and 3) symbolic differentiation. In addition to producing a prototype modeling environment, we highlight some limitations in the state of the art in tool support of simulation, and suggest ways in which some of these limitations could be overcome.

Haptic feedback can be a critical component of virtual environments used in cognitive research, rehabilitation, military training, and entertainment. A limiting factor in the innovation and the acceptance of virtual environments with haptic feedback is the time and cost required to build them. This paper presents a development environment called iAcumen that supports a new approach for programming such systems. This approach allows the developer to directly express physical equations describing the underlying dynamics. By raising the level of abstraction for the developer, we avoid many of the problems that limit the effectiveness of traditional approaches.

Digital computers permeate our physical world. This phenomenon creates a pressing need for tools that help us understand a priori how digital computers can affect their physical environment. In principle, simulation can be a powerful tool for animating models of the world. Today, however there is not a single simulation environment that comes with a guarantee that the results of the simulation are determined purely by a real-valued model and not by artifacts of the digitized implementation. As such, simulation with guaranteed fidelity does not yet exist.Towards addressing this problem, we offer an expository account of what is known about exact real arithmetic. We argue that this technology, which has roots that are over 200 years old, bears significant promise as offering exactly. the right technology to build simulation environments with guaranteed fidelity. And while it has only been sparsely studied in this large span of time, there are reasons to believe that the time is right to accelerate research in this direction.

Kaiabachev, Taha, Zhu [1] have presented a declarative programming paradigm called Functional Reactive Programming, which is based on behaviors and events. An improved system called P-FRP uses fixe ...

E-FRP is declarative language for programming resource-bounded, event-driven systems. The original high-level semantics of E-FRP requires that each event handler execute atomically. This requirement facilitates reasoning about EFRP programs, and therefore it is a desirable feature of the language. But the original compilation strategy requires that each handler complete execution before another event can occur. This implementation choice treats all events equally, in that it forces the upper bound on the time needed to respond to any event to be the same. While this is acceptable for many applications, it is often the case that some events are more urgent than others. In this paper, we show that we can improve the compilation strategy without altering the high-level semantics. With this new compilation strategy, we give the programmer more control over responsiveness without taking away the ability to reason about programs at a high level. The programmer controls responsiveness by declaring priorities for events, and the compilation strategy produces code that uses preemption to enforce these priorities. We show that the compilation strategy enjoys the same properties as the original strategy, with the only change being that the programmer reasons modulo permutations on the order of event arrivals.

Multicore processors allow manufacturers to integrate larger numbers of simpler processing cores onto the same chip with few or no changes to the processing core architecture. These processors can simultaneously execute threads from separate processes (multiprogrammed workloads) or from the same multi-threaded application (parallel workloads). The design space for on-chip memory hierarchies includes both separate and shared cache configurations, and there are performance tradeoffs for each. As the number of on-chip cores increase, accessing off-chip data can become a severe bottleneck to performance if simultaneously executing threads have different working sets, whereas executing threads from the same application can potentially reduce the demands on the memory system. At the same time, however, as the sharing degree of a cache, the number of cores sharing the cache, continues to increase, increasing access latencies and contention degrade performance [7]. Therefore, as the need for effective data sharing and on-chip data reuse become increasingly critical, shared caches become less effective or actually detrimental to performance. Threads from parallel workloads rely on synchronization to preserve data and control dependences among threads, and the threads often share some amount of data. Different parallel algorithm models and workloads have different synchronization and data sharing requirements. Achieving efficient parallel performance often depends upon minimizing the synchronization overhead, and likewise the cost of this overhead will shape the granularity of parallel tasks by determining the ratio of work to communication. Currently on homogeneous multicore processors, the fastest method of inter-core communication and data sharing will utilize the closest level of shared memory. This might be a higher level of on-chip cache as the level closest to the cores tends to be private to minimize access latencies; or, if no on-chip cache is shared, off-chip cache or main memory. The synchronization cost will include both the communication latency as well as the overhead for the synchronization method itself. We hypothesize that the addition of a smaller, software-managed shared memory with support for full/empty bit word-level synchronization will lower both the synchronization overhead and the latency of accessing shared data. We introduce this scratchpad memory for inter-core shared data on a shared-L2 cache multicore design. The scratchpad will provide fast access to shared data between the processing cores without affecting the on-chip cache organization or requiring the integration of F/E bits in the regular memory hierarchy. Load/store operations will handle data transfers to

ASIPs are designed specifically for a particular application or a set of applications. Their instruction sets must be carefully tailored to provide high performance as well as to meet non-functional constraints such as silicon area and power consumption. Traditionally, evaluation of different candidate instruction sets is all carried out through simulation. However, the growing design complexity and time-to-market pressure have rendered simulation increasingly infeasible. In this paper, we present an instruction level modeling method that can rapidly evaluates several important aspects of a selected instruction set. Experimental results show that we can prune a large number of candidate instruction sets with the model, accelerate design space exploration and alleviate the pressure on simulation