This work aims at answering to the 3D mega trend of silicon based platform and 3D wafer level packaging (3D-WLSiP). We focus on the development of architectures compliant with high volume markets for applications like mobile telecommunication. In this market, the silicon material will remain the key platform for 3D integration and has to offer the vertical interconnection as well as ultra-thin packages to fit into very slim electronic devices. We have designed both a mechanical demonstrator with daisy chains and a fully functional product based on a silicon interposer, focusing on forward and backward compatibility between Front-End and 3D packaging and the development of a complete set of advanced technological modules: - Thru-silicon-via interconnections (TSV) with copper via-mid technologies. - Ultra-thin (20 and 35 μm) chips fabrication using dicing before grinding (DBG) with 45° beveled edge and plasma stress release technology. - Thin chips stack on the TSV interposer before processing the back side (stacking first) with two different approaches. The first one is a flip chip integration based on Cu/SAC μ-bumps while the second is the Back-to-Face (B2F) way based on high topology RDL after permanent bonding of the chips face up on the interposer. Chip bonding is done with several materials either on die side with die attach film (DAF) or on interposer side using wafer level spin coated polymers. - Thin wafer handling using advanced temporary bonding process to handle the thin silicon interposer wafers during the integration based on BSI product from Brewer Science and ZoneBOND™ technology. Moreover different strategies of handling have been investigated involving high topology temporary bonding as well as carrier flip-flop approaches. - Thin wafer level packaging (TWLP) has been implemented sequentially on front side and back side of the thin resulting in a fully 3D-WLSiP module. Thermo-mechanical FEM simulation and first reliability assessment using mechanical demonstrator have been carried out and support the good mechanical behaviour of the integration. Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnection schemes in terms of resistances and yield at front side level but also at back side level after TSV exposure, RDL and bumps. Successful results of development loops have led to start processing a full functional product benefiting of the best process flow.

Fan-Out wafer level packaging (eWLP) has been proven to be a valuable solution for producing compact multi-die packages with high performances and is from now on in volume production. In this work we present a novel ultra-thin 3D-eWLP technology designed for smart-card products integrating heterogeneous ICs in a three stacked strata architecture. Individual strata of 100 μm are fabricated using the same principle than standard eWLB wafers. Specific thin wafer handling and temporary wafer-level-bonding technologies have been also developed to stack the strata one on each other involving a carrier flip-flop technique involving very tight thermal window processes. Redistribution layer consisting of polymers passivation and copper lines is formed on top of each individual stratum. Strata stacking is performed by permanent bonding polymer coating. Vertical interconnections are realized by means of through polymer via (TPV) technologies introduced at the third levels. Wafer level bumping is finally formed to assemble the dies on the frame by flip chip. A dedicated test vehicle has been designed with different combinations of daisy chains including chip metallization, fan out RDL and TPV allowing setup each brick of process and finally achieving the complete integration. A full functional demonstrator comprising two levels of memory dies on the bottom strata and one level of micro-controller dies on the top stratum has been finally fabricated and tested using this integration.

Fan-Out wafer level packaging (eWLP) has been proven to be a valuable solution for producing compact multi-die packages with high performances and is from now on in volume production[1-3]. Known good dies are rebuilt in a molding compound matrix wafer and fan out redistribution layer and bumps are subsequently built on top of the as-formed strata. In this work we present a novel ultra-thin 3D-eWLP technology designed for smart-card products integrating heterogeneous ICs in a three stacked strata architecture.