The purpose of this study is to evaluate the cybersecurity potential of the giant magnetoimpedance (GMI) effect. To fulfill this objective, it was mandatory to develop the narrowest and the most sensitive GMI element together with an uncommon polarization method that consists in injecting an internal dc bias current in the GMI film to generate a transversal magnetic field in the structure. The impedance of a Ni80Fe20/Al/Ni80Fe20 tri-layer was characterized for different thicknesses, widths, and anisotropy orientations. Each combination of these parameters offers an original outcome of the film that may be used as a specific sensor for cybersecurity purposes. This sensor can be used as an active shield that can be put over a device or included in the package in order to protect it against physical attacks, such as fault injection or invasive attacks. If one of these attacks occurs, any modification of the GMI sensing element induces a change in the impedance response allowing the detection of tampering of the secured packaging. Once the detection is confirmed, various actions can be taken, such as erasing sensitive data or resetting the device.

We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.

A structure intended to protect Integrated Circuits (IC) against physical attacks is presented. Located on the backside of a chip, it complements the countermeasures usually available on the front side of secure components. It aims at preventing attacks such as fault injection by laser illumination and can trigger an alert in case of invasive attacks by circuit edit or micro-probing. Weakening structures have been designed so as to cause the breakage of the die in case of thinning, and a metallic serpentine used as an attack witness has been thought with a maximal complexity so that an attacker cannot skirt it. These elements can be fabricated using standard packaging techniques in a wafer level integration, whether at chip or system scale. The concept of a secure System in Package (SiP) using unsecured chips is proposed, opening the perspective of components fully "secured by packaging".

In order to answer to industrial requirements and to withstand environment and functioning stresses, electronic components such as MEMS, passives, or actives, have to be packaged and encapsulated. However, as the heterogeneity and complexity of devices are increasing, versatile and scalable packaging technologies are very sought after. That is why, the additive manufacturing technologies is proposed and evaluated on silicon substrates [1]. In the present work, we have experimentally demonstrated the feasibility to package functioning components and substrates using a 3D printing polymer technology. In this study, a stereolithography printer was used to build packages and lids onto silicon substrates. Morphological, electrical, and mechanical characterizations were leaded in order to analyze the impact of the process and to assess the reliability of these packages. Finally, first aging have been carried out to evaluate the polymer degradation under thermal and ultraviolet (UV) stresses. Results were compared to initial packages achieved and will be used to improve further designs and processes. This work opens plenty of new approaches to build specific and custom packages adapted to the device and its application.

In this paper the CEA LETI proposes a silicon test vehicle and method to quantify the degradation of packaging in a biological medium. Those developments are suited for medicals devices which are potentially in contact with human cells. Different solutions of encapsulation, performed at the wafer level in clean room, are presented and compared. Test vehicles were made on silicon wafer including AlSi, Cu or WN patterns which are common used in microelectronics but known to be nonbiocompatible. The barrier properties of thin layer such as SiO 2 , Al 2 O 3 , TiO 2 , Pt and TiTiN were evaluated in PBS (Phosphate Buffer Saline) solution. Corrosion was observed thanks to optical microscope and SEM. It was shown in this study that a multilayer of SiO 2 /Al 2 O 3 /TiO 2 and Pt has successfully preserved AlSi lines from degradation during 90 days in PBS at 90°C.

In this paper we present a new approach for building specific packaging that is scalable, versatile and could be potentially cost competitive. Using polymer additive manufacturing, more commonly known as 3D printing, we set out to build customized structures and packages perfectly adapted to component dimensions and specifications. Two different 3D printing technologies, respectively called stereolithography and Fused Deposition Molding, were studied. The work described in this paper opens plenty of new approaches: device design with a customizable backend packaging process, packaging adapted to each different component, even on the same device, fast device prototyping with accurate characteristics, among others. Our main observation is that the stereolithography technology is compatible with microelectronics substrates. Another technology, fused deposition molding, was also tested, but was not well adapted to packaging components, the major incompatibilities being the inability to print on silicon and some coarser dimensions than those required for microelectronic applications. We argue that specific patterns for the printed structure and compatibility between substrate and printed material (which can be improved with surface modifications) are key requirements to obtain the expected results.

Capacitors are everywhere in electronics. They can be used for delaying, filtering, decoupling, converting, storing, etc. Various materials and technologies are used to manufacture components with different characteristics in terms of capacitance, leakage current or breakdown voltage depending on the requirements imposed by the application field. Silicon capacitors jointly developed by Ipdia and CEA-Leti combine high performances and a level of reliability that makes them suitable for high-end applications. They are also particularly appropriate for use under harsh environmental constraints such as those encountered in oil and gas prospection [1] thanks to their very good stability versus temperature [2]. In this paper, we present the developments carried out for stacking 10 chips in a package so as to obtain a 10μF capacitor capable of working continuously at 220°C during 1000h in a down-hole environment. For a first demonstrator, 100μm-thick capacitor dies were alternatively stacked and wire-bonded onto a ceramic substrate using 60μm-thick pieces of silicon as spacers [3]. Thermal tests (thermogravimetry, aging followed by shear tests) were performed in order to qualify the epoxy glue to be spread at the interfaces. A reverse ball bonding process using a fine pitch, straight bottleneck capillary was developed to obtain very low profile loops in order to prevent the wires from touching the dies above and beneath, which would have been critical for leakage. Optical profilometry and in-line electrical tests (C and I_leak measurements) were performed at each level to monitor the device functionality during the assembly. Finally Kovar lids were used to hermetically seal the packages by reflowing a AuSn preform under a N2 atmosphere. Hermeticity was measured by Residual Gas Analysis and a pressure vs. time projection was done, showing no significant pressure increase in the cavity during the lifetime of the device. Motivated by the good electrical results (capacitance within the specification, leakage current lower than 100nA) and to go further in the miniaturization and the robustness of the device, a second demonstrator was performed using a QFN package [4]. The same assembly strategy with “off-the-shelf” dies was applied on a lead frame including innovative patterns and designed with very aggressive dimensions so as to minimize the volume of the module. A new molding compound, evaluated in terms of weight loss and processability, was used to encapsulate the stacked and wire-bonded dies. After sawing, a module with a volume less than 44mm3 was obtained and showed equally good results as the first demonstrator in terms of capacitance and leakage current. A high capacitance, high reliability module was thus realized using capacitor dies and assembly materials compatible with high temperatures up to 220°C. This opens interesting prospects for the oil and gas industry since it allows drilling deeper and reaching currently inaccessible resources. The low volume of the capacitor also makes it suitable for other application fields with more drastic size constraints such as avionics or automotive.

A mechanical study of silicon interposer bow reduction, from wafer level manufacturing to large die stacking including analytical modeling, is presented in this paper. Indeed, understanding and reducing the warpage of a dissymmetrical substrate is fundamental for assembly yield and interconnects reliability. The target here is a bow less than 50 μm for a 650 mm 2 Si-interposer. This mechanical version of a power computing package demonstrator for high reliability applications integrates three top dies, whose largest is 300 mm 2 , with a 225 μm bump pitch, on a 650 mm 2 Si-interposer with a 450 μm ball pitch, itself reported on a 45 × 45 mm 2 ceramic substrate. Assembly is performed in a mass reflow oven. In this paper, the design, methodology and test vehicle process flow are firstly presented. The analytical model of the interposer bow as a function of temperature, based on the Stoney formula for small strains, is then presented. The model calibration is detailed. In this work, three levers are used to manage the bow: interposer thickness, passivation layers stress tuning, and symmetrical behavior of both faces. These actions can either shift the bow whatever the temperature, or change the bow range over temperature. Finally, the experimental results are shown. After front side manufacturing, the 725 μm thick wafer bow is reduced from 230 μm to 105 μm with optimized compressive dielectric layers. The die bow's range from ambient to assembly temperature is reduced from 50 μm to 15 μm thanks to backside processing for the 200 μm thick die. As regards the 300 μm thick die, the temperature has almost no effect on its bow which is -12 μm. Bow values after manufacturing and slopes during thermal cycles fit very well with the model developed and the assembly requirements. These results enable to fine-tune the bow and predict a very good yield and reliability for the assembly of the electrical demonstrator.

Abstract Wellness and medical area are today identified among the next big markets, and the associated roadmaps show a global trend from the benchtop to portable devices then to longer term wearable and implantable devices. For these last devices new packaging technologies need to be developed in order to satisfy both size reduction, important reliability constraints, and moderate/low costs. Two divergent identified markets have been identified:-Consumerist healthcare market associated to high volume and low cost manufacturing,-Professional healthcare market associated to low volume and high cost manufacturing. Based on these findings, we will present in this paper the main new packaging technologies developed at Léti to fit with the constraints of these markets:-In the field of wearable devices: an innovative package designed to be integrated in textiles offering low interaction with material structure and compatible with standard textile tooling and package-winding machines. A specific example of RFID tags will be presented.-In the field of implantable devices: an advanced implantable low profile silicon box for SiP including a MEMS chip and its ASIC. The emphasis will be put on the tests needed to satisfy the different constraints linked to implantability (biostability, biocompatibility).-Lastly, some generic building blocks for soft packaging will be presented, as well as the main trends in their use.

Facing demographic aging and surging demand for advanced healthcare, the global market for active medical devices has greatly expanded these last years. Furthermore, microsystem improvement in term of miniaturization offers new perspectives for medical applications. Gradually the electronic devices that were previously external invade the human body in order to improve therapy or physiological parameter measurements. However, biological medium is a new environment for such devices and the packaging has to be reconsidered taking into account new constraints. First of all it is essential to preserve the human body from toxic elements exposure that are usually present on silicon devices such as Cu or Al. Moreover, for functionality and reliability aspect it is also crucial to preserve electronics parts from corrosive substances which constitute the major part of the body. The objective of this paper is to present new strategy of packaging developed in the CEA-LETI for medical applications which include a Micro Electro-Mechanical Systems (MEMS) accelerometer and an Application-Specific Integrated Circuit (ASIC) inside a hermetic silicon box that could be embedded in a cardiac lead in order to monitor the endocardial acceleration (fig1). The electronic components are bonded on a wafer silicon interposer and covered by an additional silicon wafer which contain cavities. The wafer bonding is performed at the wafer level using eutectic AuSi solder. The gas content and hermeticity of the package were analyzed using Residual Gas Analysis (RGA) and the standard leak rate, which is assessed based on the formation of water droplet condensation in our package after 20 years, was estimated to ~6 10-13 atm.cc/s which guarantees a life time much more than 20 years. The final silicon box is encapsulated with biocompatible materials that have high conformality deposition and act as good bi-directional barrier. Materials that had been reported in literature as biocompatible and compatible with fabrication in standard clean rooms were studied. These include Al2O3, BN, SiC, DLC(a-CH), HfO2, SiN, SiO2, SiOC, TiO2 and ZnO. Biodegradation tests were performed in phosphate buffer saline at different temperature. Changes in thickness and chemical composition were monitored by variable angle spectroscopic ellipsometry and x-ray photon electron spectroscopy. Non-cytotoxic test according to in-vitro tests outlined by the norm ISO10993-5 were carried out. Finally, Helium gas permeability measurements of selected packaging layers are also provided. Figure 1

In this paper we present the work that has been carried out to stack 13 dies in a QFN package so as to obtain a super capacitor in a small volume. First the chips technology is described as well as the lead frame. Then the assembly process based on die attach film and wire bonding is explained. Finally the electrical tests of the modules are shown.

This paper is dedicated to thermomechanical simulations for the development of a solder joint fatigue model for large silicon interposers. Works were conducted in the frame of silicon platform developments for heterogeneous RF or MEMS 3D modules, where the silicon interposer could be larger than conventional WLCSP. TCoB tests have been carried out on 14.6 mm×14.6 mm×0.4 mm silicon interposer with an 800 μm pitch following JEDEC standards for board design and thermal cycles. Four configurations focused on passivation layers at solder joint/Si level have been studied. The results enable to calibrate a solder joint fatigue model for such interposers. FEM has been carried out using ANSYS software and Anand model for the solder viscoplastic behavior law. Possible models are reviewed, and our choices for a strain-based model or an energy-based model are justified. Finally a power law is used to relate experimental lifetime to damage parameters.

This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “silicon package” where the silicon interposer is either reported on P-BGA or directly assembled on board. After a materials screening with regard to warpage issue, “molding last” was studied with the selected material, including compatibility with temporary bonding debonding, bumping, sawing and report on organic substrate. A focus is made on void-less molding-underfilling process development and wafer level reliability evaluation of first level (die to wafer) interconnections and TSV subjected to thermal cycles. For this study, a molding-last approach using a dry-film lamination process has been chosen. 170μm thick dice have been assembled on 120μm thin silicon interposers having 60μm diameter TSV via-last and encapsulated with optimized wafer-level MUF process. Electrical performances of the 35μm high Cu pillars interconnections have been measured on the interposer backside thanks to TSVs and rerouting. While the daisy chains resistances remained in specifications after molding and pre-conditioning, some electrical failures appeared after 250 thermal cycles. Cross-sections have highlighted cracks in solder joints leading to the development of an improved version of the compound. Finally, a complete test vehicle with a molded-underfilled interposer reported on an organic substrate has been achieved.

3D integration relying on novel vertical interconnection technologies opens the gate to powerful microelectronic systems in ultra-thin packages answering the demand of the mobile market. Among these, die-to-wafer stacking is a key enabling technology for 2.5D as well as for 3D with technological challenges driven by, in one hand, the increase of the die surface and the number of I/Os and, on the other hand, the reduction of the vertical dimensions. In our integration scheme we have achieved flip chip stacking (or Face to Face) of 35 μm ultra-thin dies with low stand-off (< 15 μm) copper micro-bumps and tin-silver-copper solders (SAC). Ultra-thin dies are prepared using dicing before grinding (DBG) technique. After DBG, plasma stress release process is applied to the backside of the singulated chips. Copper μbump technology is challenging with this very low profile stacking since the current flip chip process is no longer adapted to this geometry and that the die flatness tolerance become very critical to obtain a high soldering yield. Process improvements have been achieved on the copper pillar fabrication itself with several metallurgy stack configurations as well as new processes using damascene techniques. Furthermore, innovative technologies have been deployed on the pick and place and collective soldering processes. Intermetallic formation during reflow process is achieved through transient liquid phase (TLP) reaction leading to thorough consumption of the tin layer and to the formation of Cu6Sn5 and Cu3Sn compounds. Capillary underfill is finally successfully applied in the narrow die-to-wafer gap by jetting technique. After optimization, electrical tests show a very high yield close to 100% over a representative number of fully populated wafers. Reliability tests have also been carried out at wafer level exhibiting no significant resistance increase or yield loss over 1000 thermal cycles between −40 and +125°C.

This paper presents a reliability study on a 15×15mm2 silicon interposer packages, 5 times larger surface than usual studies on wafer level chip scale package (WLCSP). Works were conducted in the frame of silicon platform developments for heterogeneous RF 3D modules, where the interconnections number is lower than in digital applications but the silicon interposer larger than conventional WLCSP. Several key parameters for Thermal Cycles on Board (TCoB) and Drop Test (DT) performances have been evaluated: ball type (standard SAC ball (stdb), polymer core solder balls (PCSB)), first and second passivation layers (mineral, polymers: ALX, PBO), die size (5×5, 10×10, 15×15 mm2), ball layout (full and partial matrix) and ball location (corner, main matrix). A 4-masks type test vehicle comprising copper routing, passivation and under bump metallization levels has been designed. The pitch is 800μm and the die thickness is 400μm. Different configurations have been manufactured and balled at wafer level. Reliability trials have been carried out following JEDEC recommendations for board design, TCoB and DT. Usual conditions for mobile applications have been used for reliability tests (-40°C/+125°C, 2 cycles per hour, and 1500g drops, 0.5ms half pulse duration) with continuous monitoring. With PCSB and ALX passivation, characteristic life was obtained above 300 drops and around 450 thermal cycles. Skipping balls in corner, TCoB first failure above 500 cycles is achieved with double polymer passivation and standard SAC balls. Finite element modelling is also presented to highlight the stressed areas in the different tested structures. For each factor of this extensive study, Weibull plot lifetime statistics and fracture mode analyses have been conducted, leading to a few guidelines in terms of layout, materials and structures for compliant interconnections of future large 2.5D and 3D silicon interposers reported on board.

This work aims at answering to the 3D mega trend of silicon based platform and 3D wafer level packaging (3D-WLSiP). We focus on the development of architectures compliant with high volume markets for applications like mobile telecommunication. In this market, the silicon material will remain the key platform for 3D integration and has to offer the vertical interconnection as well as ultra-thin packages to fit into very slim electronic devices. We have designed both a mechanical demonstrator with daisy chains and a fully functional product based on a silicon interposer, focusing on forward and backward compatibility between Front-End and 3D packaging and the development of a complete set of advanced technological modules: - Thru-silicon-via interconnections (TSV) with copper via-mid technologies. - Ultra-thin (20 and 35 μm) chips fabrication using dicing before grinding (DBG) with 45° beveled edge and plasma stress release technology. - Thin chips stack on the TSV interposer before processing the back side (stacking first) with two different approaches. The first one is a flip chip integration based on Cu/SAC μ-bumps while the second is the Back-to-Face (B2F) way based on high topology RDL after permanent bonding of the chips face up on the interposer. Chip bonding is done with several materials either on die side with die attach film (DAF) or on interposer side using wafer level spin coated polymers. - Thin wafer handling using advanced temporary bonding process to handle the thin silicon interposer wafers during the integration based on BSI product from Brewer Science and ZoneBOND™ technology. Moreover different strategies of handling have been investigated involving high topology temporary bonding as well as carrier flip-flop approaches. - Thin wafer level packaging (TWLP) has been implemented sequentially on front side and back side of the thin resulting in a fully 3D-WLSiP module. Thermo-mechanical FEM simulation and first reliability assessment using mechanical demonstrator have been carried out and support the good mechanical behaviour of the integration. Electrical tests have been also completed that allows comparing the performances of F2F and B2F interconnection schemes in terms of resistances and yield at front side level but also at back side level after TSV exposure, RDL and bumps. Successful results of development loops have led to start processing a full functional product benefiting of the best process flow.

RF wireless devices such as 3G/4G, Wifi, Bluethooth etc... represent today 32% of the whole WLCSP products which know a steady grow above 10% per year [1]. However, a clear trend of combining multi RF chips in one WLCSP module is emerging. This allows shorter RF connections, reduction of BOM and diminution of the overall cost. Complex and heterogeneous RF systems will become possible allowing soon tunability. A silicon package directly reported on board is a good candidate to meet these next challenges of RF WLCSP. Indeed, low cost and multi-chips interposers will soon be produced by TSV fabs or OSATs and tunables devices could be reported on them. But the direct report on board as well as the high frequency signal integrity must be first evaluated carefully. In this work, we describe promising results of silicon package based on high resistive silicon interposer encompassing 2 levels of Cu Damascene, Tx/Rx antenna, one RF chip and TSV last for 60GHz applications. A new wafer-level molding [2] is performed on front side by lamination at wafer level. On the backside of the interposer, thick Cu RDL and soft layer passivation is deposited before the balling. Just like in WLSCP, different kinds of solder balls are mounted and analyzed with respect to their size (350 or 400 μm) or type (solder or polymer/solder). The passivated interposers are diced and then reported on a PCB, thus forming the silicon package. Low Rf loss (<1dB) attenuation is demonstrated for the routing layers while the antennas exhibit a suitable gain of 5dBi over the 55–65 GHz band. The assembly characteristics between the silicon package and the board will be discussed with respect to the different chosen design rules. These first results pave the way to a new kind of smart package based on Si interposers, moving forward to more complex WLCSP RF devices.

Some 3D interconnects technologies are reviewed and discussed in this paper with respect to emerging 3D applications. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, the very fine pitch below 10μm will be mandatory for 3DIC and many options like cu-cu bonding or μ-tubes are in the race. Specific interconnects for RF/mm-waves and low volume electronics devices are also discussed with relevant examples.

We present in this paper an alternative Through-Silicon-Via approach that can meet the new requirements of Si package. In this wafer level packaging scheme, a thick silicon interposer (200 to 300μm) is directly reported on a PCB. In 200mm Si wafers, we made a two steps TSV composed of two vias: a top via and a bottom via. The top via is etched with DRIE (diameter 60μm, depth 180 μm, Aspect Ratio = AR>3), and insulated with high temperature dielectric. After dry film lithography, the TSV is partially plated with Cu limiting the process costs (short plating time, no CMP) and the stress inside the TSV. After temporary carrier bonding, the wafer is backgrinded so that 15μm remains below the bottom of the main TSV. Backside lithography and DRIE process create the bottom via (four different diameters: 10-20-30 and 40μm) to contact main TSV. A final backside Cu plating of the opening completed the process. This via bridges the gap between via-last (AR<2) and via-middle (AR>7) and combines high temperature process from via-middle and low-cost processing from via-last. The mechanical simulations show that this ″TSV bridge″ has reduced residual stresses inside the TSV. Our electrical measurements exhibit an average single TSV resistance below 10mOhms with excellent yield (∼95% on Kelvin and 82 TSV chains), and low contact resistances (4.7×10−9 Ω.cm2) extrapolated on 4 different contact diameters. This 200μm deep TSV seems therefore very promising for low-cost thick interposer applications.

In this work, innovative solutions for the full manufacturing of a camera module at the wafer scale (the wafer level camera) are presented and discussed. In order to replace the glass carrier currently used in image sensors connected with TSV (Through Silicon Via), three different integration schemes (temporary bonding, cavities etched first and cavities etched last) are proposed for the introduction of a silicon carrier with structured cavities opened over the image sensor pixel area. Excellent electrical results are demonstrated for the three solutions and the advantages and limitations of each integration scheme are discussed. In a second part a benchmarking of different materials to be used as spacers between the image sensor wafer and the optics wafers is conducted. The geometrical parameters: thickness, Total Thickness Variation (TTV) and bow of silicon, glass or epoxy wafers are compared as received and after grinding to simulate a specific focal length target. The capability to structure the three materials was also tested: laser or etching for silicon, laser for epoxy and double side sandblasting for glass. Finally an innovative solution with a direct structured spacer epoxy molding on glass is presented. In the last part, perspectives are given on the integration of a wafer level variable focal lens. Associated to emerging solutions for wafer-level auto-focus, the potential of low cost polymer via filling through the optical stack is discussed.