Nanoimprint lithography is a newly developed patterning method that employs a hard template for the patterning of structures at micron and nanometerscales. This technique has many advantages such as cost reduction, high resolution, low line edge roughness (LER), and easy operation. However, resist peeling, defects, low degree of planarization, and low throughput issues present challenges that must be resolved in order to mass produce advanced nanometer-scale devices. In this study, the new approach of using spin-on hard mask materials under the resist to modify its adhesion during a UV irradiation process in nano imprint lithography was proposed to increase process latitudes. The performance of this process is evaluated by using step and flash imprint lithography. We expect that these spin-on hard mask materials (NCI-NIL-U series) under organic resist will be one of the most promising materials in the next generation of nano imprint lithography.

Nanoimprint lithography is a newly developed patterning method that employs a hard template for the patterning of structures at micro- and nanometer scales. This technique has many advantages such as cost reduction, high resolution, low line edge roughness (LER), and easy operation. However, resist peeling, defects, low degree of planarization, and low throughput issues present challenges that must be resolved in order to mass produce advanced nanometer-scale devices. In this study, the new approach of using a silicon-containing spin-on hard mask underlayer material with high adhesion by reacting methacrylate groups of the underlayer to the acrylate groups of resist material during ultraviolet irradiation was demonstrated to obtain the excellent patterning dimensional accuracy and increase the process latitudes. The performance of this process is evaluated by using step and flash imprint lithography. The obtained high adhesion between the underlayer and resist material was found to lead a silicon-containing underlayer material to excellent patterning dimensional accuracy and 80 nm straight profiles. We expect that the silicon-containing a spin-on hard mask material under organic resist will be one of the most promising materials in the next generation of nanoimprint lithography.

The current optical photolithography technology is approaching the physical barrier to the minimum achievable feature size. To produce smaller devices, new resolution enhancement technologies must be developed. Double-exposure lithography has shown promise as a potential pathway that is attractive because it is much cheaper than double-patterning lithography and can be deployed on existing imaging tools. However, this technology is not possible without the development of new materials with nonlinear response to exposure dose. The performance of existing materials such as reversible contrast enhancement layers (rCELs), and theoretical materials such as intermediate state two-photon (ISTP) and optical threshold layer (OTL) materials in double-exposure applications have been investigated through computer simulation. All three materials yielded process windows in double-exposure mode. OTL materials showed the largest process window (depth of focus (DOF) 0.14 mu m, exposure latitude (EL) 5.1%). ISTP materials had the next-largest process window (DOF 0.12 mu m, EL 3.2%), followed by the rCEL (0.11 mu m, 0.58%). This study is an analysis of the feasibility of using the materials in double- exposure mode. (C) 2009 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3095589]

193 immersion lithography has reached its maximal achievable resolution. There are mainly two lithographic strategies that will enable continued increase in resolution. Those are being pursued in parallel. The first is extreme ultraviolet (EUV) lithography and the second is double patterning (exposure) lithography. EUV lithography is counted on to be available in 2013 time frame for 22 nm node. Unfortunately, this technology has suffered several delays due to fundamental problems with source power, mask infrastructure, metrology and overall reliability. The implementation of EUV lithography in the next five years is unlikely due to economic factors. Double patterning lithography (DPL) is a technology that has been implemented by the industry and has already shown the proof of concept for the 22nm node. This technique while expensive is the only current path forward for scaling with no fundamental showstoppers for the 32nm and 22nm nodes. Double exposure lithography (DEL) is being proposed as a cost mitigating approach to advanced lithography. Compared to DPL, DEL offers advantages in overlay and process time, thus reducing the cost-of-ownership (CoO). However, DEL requires new materials that have a non-linear photoresponse. So far, several approaches were proposed for double exposure lithography, from which Optical Threshold Layer (OTL) was found to give the best lithography performance according to the results of the simulation. This paper details the principle of the OTL approach. A photochromic polymer was designed and synthesized. The feasibility of the material for application of DEL was explored by a series of evaluations.

The current optical photolithography technology is approaching the physical barrier to the minimum achievable feature size. To produce smaller devices, new resolution enhancement technologies must be developed. Double exposure lithography has shown promise as potential pathway that is attractive because it is much cheaper than double patterning lithography and it can be deployed on existing imaging tools. However, this technology is not possible without the development of new materials with nonlinear response to exposure dose. The performance of existing materials such as reversible contrast enhancement layers (rCELs) and theoretical materials such as intermediate state two-photon (ISTP) and optical threshold layer (OTL) materials in double exposure applications was investigated through computer simulation. All three materials yielded process windows in double exposure mode. OTL materials showed the largest process window (DOF 0.137 mu m, EL 5.06 %). ISTP materials had the next largest process window (DOF 0.124 mu m, EL 3.22 %) followed by the rCEL (0.105 mu m, 0.58 %). This study is an analysis of the feasibility of using the materials in double exposure mode.

Step and flash imprint lithography (SFIL) is low cost, high resolution patterning process and has found its way into a multitude of front end of the line (FEOL) and back end of the line (BEOL) applications. SFIL-R, a reverse tone variant of SFIL, and imprintable dielectrics are examples of such applications, and both require the design of specialized, silicon-based materials. Polyhedral oligomeric silsesquioxane (POSS) liquids were modified through a dual functionalization strategy to introduce photosensitive acrylate and thermally curable benzocyclobutane (BCB) groups to the molecule. The optimal functional group ratio was observed to be 3:5 acrylate to BCB, and the result was an imprintable dielectric with good mechanical properties and minimal post-exposure shrinkage. Thermal gravimetric analysis (TGA) revealed good thermal stability with minimal mass loss under annealing conditions of 400°C for 2 hours. Si-14 was designed to be a non-volatile, etch-resistant planarization layer for SFIL-R application. A polydimethylsiloxane (PDMS) derivative was modified to introduce acrylate functional groups and side branching for photosensitivity and low viscosity, respectively. Characterization of the material showed ideal planarization characteristics - low volatility (0.77 Torr at 25°C), low viscosity (15.1 cP), and minimal post-exposure shrinkage (5.1%).

Advanced integrated circuits require eight or more levels of wiring to transmit electrical signal and power among devices and to external circuitry. Each wiring level connects to the levels above and below it through via layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around 20 process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. Through use of a template with two tiers of patterning, a single imprint lithography step can replace two photolithography steps. Further improvements in efficiency are possible if the imprint material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.

The dual damascene process used to generate copper interconnects requires many difficult processing steps. Back End Of Line (BEOL) processing using Step and Flash Imprint Lithography (SFIL) on a directly patternable dielectric material can dramatically reduce the number of processing steps. By using multi-level SFIL rather than photolithography, two levels of interconnect structure (trench and corresponding via) can be patterned simultaneously. In addition, the imprinted material can be a imprintable dielectric precursor rather than a resist, further reducing the total number of steps in the dual damascene process. This paper presents progress towards integrating multi-level SFIL into a copper CMP process flow at ATDF, Inc. in Austin, Texas. Until now, work has focused on multi-level imprint process development. This report focuses on the development of new imprintable dielectric precursors for use with the dual damascene imprint process. SFIL compatible dielectric precursors were synthesized and characterized for integration into the ATDF copper CMP process flow. SFIL requires properties not found in currently available semiconductor dielectrics such as low viscosity and rapid photo-induced polymerization. Inorganic/organic hybrid materials derived from sol-gel chemistry and polyhedral oligomeric silsesquioxane (POSS) structures show promise for this application. The properties of three different dielectric layers are compared. The viability of each material as an interlayer dielectric is discussed and the results of multi-level patterning, metal fill, and polish are shown.

Advanced microprocessors require several (eight or more) levels of wiring to carry signal and power from transistor to transistor and to the outside world. Each wiring level must make connection to the levels above and below it through via/contact layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace two photolithography steps. Further efficiencies are possible if the imprint resist material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.