This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum 2 and 0.124 mum 2 . SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T inv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124 mum 2 cell to meet low power application requirements.

For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mu m(2). Record NMOS/PMOS drive currents of 1000/575 mu A/mu m, respectively, have been achieved at 1 nA/mu m off-current and 1.1V V-dd with a low cost process. With this high performance transistor, V-dd can be further scaled to 1.0V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L-gate=30nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.