Recent advancements in qubit manipulation in quantum dot arrays, as well as in the classical/quantum co-integration of FD-SOI spin-based quantum circuits shed light on an industrialization path for large-scale quantum computing. We present this path to designing and engineering good qubits using technology that is as close as possible to the most advanced industrial FD-SOI nodes. We then investigate qubit design accounting for the constraints arising from the established industrial fabrication process. More precisely, we repurpose the W vias and, in a single contact patterning step, define the gates that enable to define the electrochemical potential of quantum dots (QDs), as well as the W vias that control the coupling barriers between adjacent QDs. We present simulation-based and experimental results on the individual coupling control of QDs in arrays fabricated on the industrial 28 nm FD-SOI technology. We present detailed wafer-level transfer characteristics of each barrier implemented on a 1x3 linear array at room temperature and at 2K. These results demonstrate that the vias behave like MOSFET gates, providing effective electrostatic control over the silicon channel. This validates the compatibility of the 28 nm FD-SOI industrial route with essential requirements for demonstrating a two-qubit gate.

This study reports new preliminary results on fully co-integrated 28 nm FD-SOI UTBB phase change memories (PCM) programmed at room temperature (RT) and cryogenic temperature (CT). The PCM is a germanium, antimony, tellurium (GST) compound type which is found to be functional at 77K with multi-state switching without additional operating requirements compared to the ambient temperature. As the phase change memory is temperature dependent, drift tests are also performed to track the change in resistance over time after programming the pulses to estimate drift coefficients. An interesting feature is that using the same programming bias conditions, the drift coefficient is three times lower at 77K with an improvement in the Ion/Ioff ratio. These results are very encouraging and open the door to the PCM in applications both at high temperatures (e.g. automotive) and at very low temperatures (e.g. space, quantum).

this work, a low-cost artificial intelligent analog synapse using commercial 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS technology was applied in a computing-in-memory (CIM)-based neural network (NN) and co-optimized from the device level to the system level. Through read-and-write scheme optimization, the synapse realized the nonlinearity of 0.14/0.90 and the I-Pot./I-Dep. ratio of 4.3:1, as well as excellent retention and uniformity. The comprehensive performance of the CIM-based NN system, including accuracy, energy, and latency, was evaluated by the open-source simulation tool NeuroSim+. Based on the device and system co-optimization, the CIM-based NN system can achieve an accuracy of 92% and energy consumption of only 0.45 mJ during online training. This work revealed the feasibility of the FDSOI FET-based synapse as a high performance and low cost solution for the CIM-based NN system.

Seeking to circumvent conventional computing bottlenecks, hardware alternatives, from brain-inspired designs to cryogenic quantum systems, necessitate integrating emerging non-volatile memories. Yet, the immaturity and unreliability of cryogenic-compatible memories hinder scalable computing advancements. This study characterizes 28 nm FD-SOI substrate-embedded Ge-rich Ge2Sb2Te5 phase change memories (ePCMs) down to 12 K to overcome these hurdles. It reveals that ePCMs is cryogenic compatible and can encode multiple resistance states with minimal drift, essential for advanced computing solutions. Through simulations, the ePCM’s impact on a spiking neural network (SNN) performing MNIST classification is evaluated. The SNN maintains high accuracy for extended periods of 2 years at cryogenic temperatures, while an accuracy drop of 10.8% is observed at room temperature. These results highlight the potential of multilevel ePCMs in brain-inspired cryogenic computing applications, offering a promising avenue for the evolution of unconventional computing systems.

We present a novel dual isolation scheme with standard STI and + a single diffusion break local oxidation of the film in FD-SOI technology, extending its highly efficient back-bias capability. For the first time, both Forward and Reverse modes are demonstrated on the same ring-oscillator devices from 28nm FD-SOI technology. A large range of performance/leakage tuning is achieved with record voltage drop across NMOS and PMOS wells ranging [−3V,+5V]. Leveraging this capability, we experimentally demonstrate a process-induced variability reduction of ~50% on Frequency using independent NMOS/PMOS back-biasing in several regimes.

This paper presents an autonomous road traffic monitoring Edge AI SoC implemented in 18nm FD-SOI CMOS. The SoC includes a RISC-V CPU, a 128 Processing Elements (PE) Single Instruction Multiple Data (SIMD) Tensor Processing Unit (TPU) AI accelerator, with QVGA and control interfaces. It uses Adaptative-Body-Bias (ABB) process and temperature compensation. The circuit operates within 0.5 to $0.87 \mathrm{~V},-40$ to $140^{\circ} \mathrm{C}, 50$ to 500 MHz ranges. The TPU efficiency energy per inference and latency are $3.52 \mu \mathrm{~J}$ and 0.616 ms when running MobileNet v1 stripped by 2 layers, and $14.8 \mu \mathrm{~J}$ and 2.27 ms when running traffic monitoring application. For this latter application, the circuit total power is 6.38 mW at 15 fps 0.5 V supply.

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This paper presents an autonomous road traffic monitoring Edge AI SoC implemented in 18nm FD-SOI CMOS. The SoC includes a RISC-V CPU, a 128 Processing Elements (PE) Single Instruction Multiple Data (SIMD) Tensor Processing Unit (TPU) AI accelerator, with QVGA and control interfaces. It uses Adaptative-Body-Bias (ABB) process and temperature compensation. The circuit operates within 0.5 to 0.87 V, -40 to 140 degrees C,50 to 500 MHz ranges. The TPU efficiency energy per inference and latency are 3.52 mu J and 0.616 ms when running MobileNet v1 stripped by 2 layers, and 14.8 mu J and 2.27 ms when running traffic monitoring application. For this latter application, the circuit total power is 6.38 mW at 15 fps 0.5V supply.

Seeking to circumvent the bottleneck of conventional computing systems, alternative methods of hardware implementation, whether based on brain-inspired architectures or cryogenic quantum computing systems, invariably suggest the integration of emerging non-volatile memories. However, the lack of maturity, reliability, and cryogenic-compatible memories poses a barrier to the development of such scalable alternative computing solutions. To bridge this gap and outperform traditional CMOS charge-based memories in terms of density and storage, 28 nm Fully Depleted Silicon on Insulator (FD-SOI) substrate-embedded GexSbyTez phase change memories (ePCMs) are characterized down to 12 K. The multi-level resistance programming and its drift over time are investigated. The ePCM can be programmed to achieve and encode 10 different resistance states, at 300 K, 77 K, and 12 K. Interestingly, the drift coefficient is considerably reduced at cryogenic temperatures. Cycle-to-cycle programming variability and resistance drift modelling are carefully used to forecast and evaluate the effect of resistance evolution over time on a fully connected feedforward spiking neural network (SNN) at different temperatures. System-level simulation of a Modified National Institute of Standards and Technology database (MNIST) classification task is performed. The SNN classification accuracy is sustained for up to two years at 77 K and 12 K while a 7–8% drop in accuracy is observed at 300 K. Such results open new horizons for the analogue/multilevel implementation of ePCMs for space and cryogenic applications.

The enablement of a high-density memory array in a System on Chip (SoC) is a great opportunity to overcome the Von-Neuman bottleneck in computation, especially for applications at the edge. In this work, we will show that a dense array based on 0.019μm2 Phase-Change-Memory (PCM) cell, embedded in 18nm FD-SOI CMOS process, typically operated in differential mode, can be operated in single-ended mode for effectively storing Neural Network (NN) weights on a wide range of mission profiles. Differently from the previously adopted differential approach, the single-ended is less resilient to PCM reliability mechanisms, so proper algorithm and design optimizations have been carried out to provide a reliable behavior.

In this paper, the competitive advantage of Phase Change Memory (PCM) with BJT selector in 18nm FDSOI technology is explained. Starting from Microcontrollers requirements and architectures, the impact of technology features and device flavor in high performance and low-cost Microcontrollers is analyzed in section I, while the peculiarities of ePCM cell with BJT selector and its high-density advantages vs other NVM Back End solutions are illustrated in section II. The ePCM NVM IP Architecture constraints are presented in section III with particular emphasis on the need to split the arrays in Tiles. In section IV the impact of BJT selector in Reading Architecture is discussed showing the limits of classical solution and introducing a reading technique using multiple voltage domains sensing for Low Power Micros. Experimental results on a dedicated Test Vehicle are illustrated in section V.

This work demonstrates for the first time the 3D sequential integration of CMOS over CMOS with advanced metal line levels (28nm Cu + ULK). The bottom tier consists of a 28nm FDSOI industrial wafer with 4 metal lines. A bevel contamination wrap module allows the return of the wafer to Front End Of Line (FEOL) environment required for achieving high performance top FET Si CMOS processing. Additionally the doped poly-Si ground plane introduced enables top FET dynamic back-biasing and effective DC and HF isolation with underlying metal lines. Finally, this 3DSI platform demonstrates functional top, bottom, and 3D ring oscillators as well as a pixel with single exposure flicker-free High Dynamic Range capability obtained thanks to the stacking of an additional circuit over a bottom 3T-pixel.

In this work we report a study and a co-design methodology of an analog SNN crossbar output circuit designed in a 28nm FD-SOI technology node that comprises a tunable current attenuator and a leak-integrate and fire neurons that would enable the integration of emerging non-volatile memories (eNVMs) for synaptic arrays based on various technologies including phase change (PCRAM), oxide-based (OxRAM), spin transfer and spin orbit torque magnetic memories (STT, SOT-MRAM). Circuit SPICE simulation results and eNVM experimental data are used to showcase and estimate the neurons fan-in for each type of eNVM considering the technology constraints and design trade-offs that set its limits such as membrane capacitance and supply voltage, etc.

Intrinsic robustness against electrostatic discharge (ESD) like HBM or CDM is a major concern for the reliability and functionality in advanced CMOS FD-SOI technology and especially for non-volatile memory (eNVM). And it is well known that device characterizations are a first step of an ESD investigation. Thus, this R&D study the experimental results from 100 ns to 1 ns transmission line pulse (TLP-VFTLP) on 1T1R phase change memory (PCM) at 300 mm wafer level and at room temperature are reported here. Two types of devices are fabricated and characterized in the standard fully depleted (FD) silicon-on-insulator (SOI) with ultra-thin body and BOX (UTBB). These devices have no additional technological step and are embedded in the final memory cell topology with its selector NMOS transistor. The idea is to evaluate the behaviour of the 1T1R device under transmission line pulse stress with different stress durations. TLP/VFTLP I-V curves are reported and discussed along with post-DC responses to determine the magnitude of the phase change generated by the ESD pulse. These characterizations are important for automotive, micro-controllers, neuromorphic computing and spatial applications depending on their dedicated mission profiles at room or cryogenic temperature.

We successfully developed new devices and new features in the 18nm FDSOI technology for addressing the low power and the low leakage demands of Micro-Controller Units (MCUs). In a quadruple fully mixable Vt offer, 80% speed enhancement and 2x leakage reduction are demonstrated at $0.6 V V_{dd}$ vs the fastest and vs the less-leaky 28nm FDSOI devices, respectively. Low leakage device options have been built for all device families of this Triple Gate Oxide (TGO) platform (i.e thin: SG – medium: EG – thick: eZG), achieving 10pA/μ m for SG/EG transistors and 1pA/μm Idoff for 3.3V eZG ones without adding any mask nor process cost. For SRAM, the high-density $0.102 \mu m^{2}$ SRAM bitcell has been carefully optimized and, in addition, an innovative Zero-power $0.532 \mu m^{2}$ SRAM (ZpSRAM) is proposed for the first time. As a result, record-low retention leakage of 0.6pA/cell and 30fA/cell are reported respectively for those two bitcells, completing the list of benefits brought to the 18nm FDSOI device suite to fulfill ULP/ULL design requirements.

The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

In the first part of this two-part article, implant-induced strain relaxation has been successfully demonstrated on a common strained silicon-on-insulator (SSOI) platform. In this second part, based on an SSOI platform that could enable the cointegration of highly tensile-strained Si n-channel field-effect transistors (nFETs) and compressive-strained SiGe p-channel FETs (pFETs) on the same substrate for both logic and 5G RF circuits, we here propose a comb-like device structure within the strained SOI platform for further improvement in the electrostatic, dc, and RF performances over the unstrained SOI FinFETs counterpart. It is demonstrated that the peak ${G}_{\text {m}}$ of strained comb-like Si nFETs can be improved by 35% over unstrained n-type FinFETs SOI. The improvements of ${f}_{\text {T}}$ by 22% and ${f}_{\text {max}}$ by 36% over no-comb devices are also observed. Furthermore, the linearity of ${f}_{\text {T}}$ and ${f}_{\text {max}}$ has been greatly improved by introducing forward body biasing on the comb-like device structure.

Ge-rich and N-doped Ge-Sb-Te thin films and patterned structures for memory applications are investigated in situ during annealing up to 500 degrees C with a heating rate of 2 degrees C/min using synchrotron x-ray diffraction. The initial material is amorphous. Under these annealing conditions, Ge crystallization occurs at 340 degrees C and precedes the one of cubic Ge2Sb2Te5 by about 15 degrees C. In situ monitoring of diffraction allows for a quantification of crystallized quantity, grain size and elastic strain during the material transformation. Increasing N doping reduces the amount of crystallized Ge and Ge grain size. These results bring important insights into the multiphase crystallization of Ge-rich GST phase change materials for memory applications.

One of the most promising Embedded Phase Change Memory (ePCM) integration scheme is the wall architecture, which relies on the dedicated Heater element to thermally switch the device. A good control of this element is a key factor to satisfy the performance requirements of the automotive market. In this paper, the optimization of TiSiN Heater system in $0.019\mu \mathrm{m}^{2}\text{ePCM}$ cell realized with 28nm FDSOI technology is extensively reported. Key fabrication parameters defining heating efficiency are investigated, covering a large range of Heater resistance. Their impact on $e$ PCM reliability of elementary device and 16MB memory array, considering both retention and endurance, is characterized and the key role played by Heater is demonstrated, opening a path to scaled programming currents. Finally, TiSiN ALD deposition process is proposed as the solution to improve uniformity and scalability of Heater resistance. As Heater is the variable controlling the whole system, this approach guarantees the robustness of $e$ PCM technology for automotive grade-0 applications.

Fabrication and electrical characteristics of a new BJT selector enabling a 1T1R embedded phase change material (ePCM) memory cell of 0.019µm 2 are extensively reported in this paper. A smart process, leveraging the specific feature of the FDSOI substrates with its thin buried oxide (BOX) has been developed to create an innovative isolation wall between bitlines (BL) and to totally suppress the parasitic BL-to-BL leakage. A current of 300µA at V EB =1.6V and a leakage as low as 8pA/cell at V BE =3.6V, 165°C were achieved. Compared to its MOS selector counterpart, -48% cell area reduction is obtained at same driving current, demonstrating the high density and the cost competitiveness of this FDSOI BJT selector solution. Finally, a shrunk BJT-ePCM cell of 0.015µm 2 , which is the smallest 1T1R eNVM reported to date, is demonstrated for the first time.